ACO Interface Table of Contents Introduction Please note the architecture of the b2b system (click). Please note the minutes of the CCT decision decision meetin...
Concept B2B Lite Table of Contents Principle Figure: Extraction (R1) and injection (R2) rings are operated at different harmonic numbers. Shown are filled buck...
Concept B2B Lite This is an outdated document! Table of Contents Plan A Reminder Figure: Sketch for B2B transfers from SIS18 to SIS100, figure from PhD Bai. ...
'Deprecated' Documents Table of Contents B2B Lite * 1st description of the principle (click) * planning for machine experiment 2021 (click) Original Appro...
Documentation Some documentation is given here. This is not structured but just a collection of various things. * Documents * HOW TOs Main.DietrichBeck ...
Get Values and Analyzed Values Table of Contents Introduction As with set values, there are multiple sets of get values. In addition, there are results of the an...
How To: Towards Complete Kicker Timing Introduction This page tries to summarize my knowledge (db, December 2021) on kicker timing at GSI. The focus is on hardwa...
How To: Bunch to Bucket Transfer System Ein Überblick System am Beispiel von SIS18 Das Bunch 2 Bucket Transfer System ist eine Anwendung des General Machine Ti...
How To: Bunch to Bucket System Betrieb Kurzfassung * nur Extraktionsring: Modus einstellen, B2Extraction für schnelle Extraktion zu einem Cave oder B2Coasti...
User Interfaces Table of Contents Introduction This page just describes the user interfaces. All command line interfaces (CLI) just require a keyboard. Navigati...
How To: Fehler Einleitung Nur ein Liste mit Fehlern und was man tun koennte. Fehler des B2B Systems * Frequenzwert nicht im gueltigen Bereich * Umlauff...
How To: Firmware, Tests and Development Status August 2017 Introduction This page summarizes the status of development and firmware for the Bunch to Bucket Tra...
How To: Install Frontend Introduction This how to describes steps necessary to install and commission a frontend Preparation * CCT, Machine Model and Service...
HOW TOs This is just a unrevised collection. The purpose is to write down some things, before we forget them... Related to Users and Operation * Betrieb ...
Proof of Principle: Setup at SIS18 and ESR Table of Contents Introduction The idea is to setup and perform a proof of principle machine experiment in the 2021 be...
Shopping List for the 2021 Beamtime Summary * ACC network: extension or new installation @ SIS, ESR, CRYRING, PHELIX; in progress * WR network: extension ...
Triggering of MIL Based Equipment Informative: Triggering of FAIR style White Rabbit based equipment has already been considered, see approved technical concept, ...
Older News * 11 Mar 2019: very little personnel: some conceptual work (maybe) * 04 Jul 2017: no personnel: work package frozen * 09 Mar 2017: request for...
Realtime Communication Table of Contents Introduction The b2b system is a distributed system where distinct components are required to communicate in hard realti...
Setup Table of Contents Schematic View Figure: Extraction (top) and injection (bottom). The figure above depicts the setup. Group DDS system generate H=1 cloc...
Slow Control and Monitoring Table of Contents Introduction The B2B system is a fairly simple device with a few inputs and outputs connected via interface boards ...
Sub Nanoseconds Phase Fit Method The sub ns phase fit algorithm can increase the preceision of time stamped data points from a periodic signal to values below th...
Trigger Decision Module The Trigger Decision Modules (TDM) has the task of taking the trigger decision. It also takes care of all sort of delays, time of flight a...
June 2019: Frequency Beating on Office Desk Table of Contents Setup In June 2019, first measurements have been done using the following setup in my office * ...
June 2022: Bunch to Bucket SIS18 ESR V2 Table of Contents Introduction A machine experiment is performed on 29 June. The experiment has two aims. First, bunch...
December 2022: Testing Precision in the Integration System Table of Contents TL;DR If you are not interested in details: * the precision 'as is' exceeds speci...
June 2023: Testing Precision in the Production System Table of Contents TL;DR If you are not interested in details: The precision 'as is' seems to exceeds specif...
June 2023: Testing Magnet Probe Signals at CRYRNG Extraction Table of Contents TL;DR Actual kicks can be detected without problem. Getting precise timing on the ...
August 2023: Re Testing Magnet Probe Signals at CRYRNG Extraction Table of Contents TL;DR Actual kicks can be detected without problem. Getting precise timing on...
November 2023: Testing Magnet Probe Signals at SIS18 Extraction Table of Contents TL;DR Test on 3 November 2023. Seems to work. Introduction The b2b system uses...
November 2023: Testing Stability at SIS18 Extraction Table of Contents TL;DR Test on 9 November 2023. Seems to work. Introduction The data presented here have b...
December 2023: More Stability Tests Table of Contents Introduction Some data of the 2023 engineering run have been looked at in more detail. All (!) Phase Measu...
December 2019: Frequency Beating in RRF Supply Room Table of Contents Setup In December 2019 measurements have been done using the following setup in the RRF sup...
November 2020: Dry Run Table of Contents Introduction In November 2020 the B2B system was tested during a dry run. The following main features were deployed ...
January 2021: Dry Run Table of Contents Introduction In January 2021 the B2B system was tested during a dry run. The following new features have been deployed a...
2021 Feb 21: 'Old' Timing Generator Table of Contents Introduction The b2b system was operated 'dry' in parallel to standard machine operation for bunch to coast...
2021 Apr 13: SIS18 Extraction Kicker with the Bunch 2 Bucket System Table of Contents Introduction On 13 April 2021, it was possible to perform a ~4 hour 'dry ru...
May 2021: Test Operation and First Real Bunch to Bucket SIS18 ESR Table of Contents Introduction The bunch to bucket transfer system has been used for almost ...
June 2022: Bunch to Bucket SIS18 ESR Table of Contents Introduction A machine experiment is performed on 2 June. The aim of this experiment is to repeat the e...
June 2022: Bunch to Bucket ESR CRYRING Table of Contents Introduction A machine experiment has been performed on 7 June. The aim of this experiment was to tes...
Tests and Masurements Table of Contents Bunch 2 Bucket Lite * More Stability Tests (01/2024) * Testing Stability at SIS18 Extraction (12/2023) * Testing...
List of To Do Items To Do List This is an informal To Do list by the b2b Team. The list is no project planning, but might be useful for project planning. To Do ...
Bunch to Bucket Transfer System This work package was frozen from mid 2017 to mid 2019 The purpose of the Bunch to Bucket (B2B) transfer system is to transfer i...
FEC Filesystem This document describes filesystem and boot process for a FESA frontend computer (commonly referred to as FEC). General Boot Process * bios exe...
Deliver FESA3 equipment at GSI In order to run your equipment, you first need to deliver it to the testing directory. NOTE: To have the writing rights to deploy a...
Deliver FESA3 euipment In order to run your equipment, you first need to deliver it to the testing directory. NOTE: To have the writing rights to deploy a Deploym...
Delivery of FESA Software to the MCS On the asl cluster: 1 Add the needed FEC and instance file for the MCS in Eclipse FESA Plugin. (e.g. scul024f ) 1 Build...
Delivery of FESA Software to the MCS On the asl cluster: 1 Add the needed FEC and instance file for the MCS in Eclipse FESA Plugin. (e.g. scul024f ) 1 Build...
CRYRING CRYRING is a heavy ion storage ring which will be used for FAIR prototype testing as well as for atomic physics experiments for the SPARC collaboration. ...
GSI Timing Team Core members of the GSI Timing Team are: F. Ameil (associated): work package lead (FAIR) D. Beck: operation, tools and docs, legacy stuff for UNIL...
Acronyms These acronyms are focused on the timing system, but may contain other acronyms of the accelerator complex as well. Unclear Acronyms acronyms to be clar...
BuTiS Receiver Station The BuTiS receiver station are maintained by the RF group, contact persons are P. Moritz or B. Zipfel. Setup Figure 1: BuTiS receiver sta...
White Rabbit, BuTiS, Clocks and Time Introduction Two systems exist for distribution of time stamps and clocks: 1. The General Machine Timing System provides ...
Clock Master Production This page documents the configuration of the Clock Master. Please note the corresponding How To. Introduction The Clock Master is the sou...
Clock Master Other This page documents the configuration of the Clock Master for the other White Rabbit networks (not 'Production'). Introduction The Clock Mast...
The Timing System and its Context in the Accelerator Control System What is described here has been compiled from the Common Specifications for the Accelerator Co...
Gateway Data Master UNILAC PZ (dm unipz) Introduction "dm unipz" is the interface between the White Rabbit based Data Master und the MIL based UNILAC 'Pulszentr...
The XML Format Used by the Data Master The DM uses an XML format to describe a schedule. Presently (09/2014), this format depends on implementation details. A (no...
Deprecated Documents This is just a unrevised collection of outdated or deprecated documents. * Feature List for a Timing Receiver Node at GSI/FAIR (09/2014)...
Deprecated HOW TOs This is just a unrevised collection of outdated or deprecated HOW TOs. Timing Receivers * Building and Installation * HOW TO: Instal...
Etherbone Performance Measurements Introduction Access to Wishbone (WB) slaves in the FPGA from the host system is a prominent use case for the accelerator contr...
SCU Kernel Task Switching Latency Introduction The hardware group (thx to Stefan!) has investigated task switchting / preemption on the SCU kernel with RT patch ...
Pseudo SRAM Access from lm32 Introduction The W968D6DA provides 256Mbit (32MByte) of Pseudo SRAM (datasheet). It provides 32 bit address width and 16 data lines....
WR ZEN aka SSK Introduction The timing team (TOS) operates a couple of distinct White Rabbit networks. The most important one is a network called production, tha...
Report: Latency and Loss of Timing Messages in the Timing System Introduction Starting in October 2019 the ECA Tap module was added to the gateware of a few dedi...
Saftlib Latency Measurements During the startup of the accelerator in February 2021, issues have been observed with the so called function generator (FG): Occasio...
Documentation Some documentation is given here. This is not structured but just a collection of various things. * Documents * HOW TOs * Releases * Cur...
Feature List for Add On boards of Timing Receivers at GSI and FAIR This page lists some hardware features for add on boards. Such add on boards are mezzanine boar...
Black_Cat1 Mezzanine Board The Black Cat mezzanine board extends the PEXARIA5 board with I/Os. However, the WR1 connector on Black Cat is no longer used, as the W...
Connection to EE Labor This is just a temporary document, to be replaced by some proper documentation. Note on calculating cable lengths The cable length has bee...
Feature List for Timing Receivers at GSI and FAIR This page lists some hardware features for timing receivers at GSI and FAIR. Some recommended features will beco...
Gateware and Firmware Gateware and firmware are provided with releases. * Gateware: synthesized (V)HDL code * Firmware: compiled code for the lm32 soft CPU ...
The FAIR Timing Master in the "Betriebsgebäude" BG This is a collection of documents related to the FAIR Timing Master in the "Elektronikraum". Equipment Rack5...
Timing Network Networks There are several instances of timing networks on the campus. * Productive * production: everything starting with the end of TK ...
PEXARIA5DB The PEXIARA5DB is a mezzanine card for a PEXARIA5 carrier board. It exists in two variants. * PEXARIA5DB1, with IDC connector for LVDS signals: sche...
Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...
Booster Test December 2021 TL;DR For 'booster mode': * timing the beam transfer from UNILAC to SIS18 works with ~98% efficiency, if rf conditioning at UNILAC ...
Reports and Measurements This page serves to collect reports and measurements on the GMT. Booster Test * Timing events during 1st Booster Mode Test (2021 12 1...
FMC Module SIXIO2 The FMC module SIXIO2 has been designed by Jan Hoffmann / EE. It's purpose is simple I/O. * Info by EE: Some figures and specs * Sixio2_SC...
Simple API For Timing (SaftLib) Simple API For Timing (SAFT). The design and implementation of SaftLib is a major project. Introduction The key features SaftLib ...
Doomsday Release (DEPRECATED) Previous releases are Asterisk, Balloon and Cherry. This release is replaced by Enigma. New features and bug fixes in Doomsday Rel...
How To: Etherbone with Wireshark Introduction Wireshark might be useful when you need to inspect Etherbone packages sent via Ethernet, see here. Here are a few h...
Enigma Release (DEPRECATED) Previous releases are Asterisk, Balloon, Cherry and Doomsday. This release has been replaced by release Fallout. New Features and Bu...
Etherbone Introduction The idea behind the EtherBone (EB) protocol is to extend the reach of the embedded Wishbone (WB) V4 System on a chip (SoC) bus system to r...
Timing Messages Format of a Timing Message Timing messages is a term describing the input to a Timing Receiver (TR) that possibly leads to generation of a so cal...
Event Numbers Overview Event numbers serve as IDs for actions performed by the control system. Existing Facility Information about event numbers used by the ex...
Fallout Release Previous releases are Asterisk, Balloon, Cherry, Doomsday and Enigma New features and bug fixes in Fallout Release * 2020 Aug 31: v6.0.0 alph...
How To: Accessing ACO Frontends Using ACO Tools Introduction This how to is just intended as a primer for non specialists. Disclaimer: There are many, many possi...
GPSDO The GPSDO serves as a primary reference time source for the timing system. Amongst the interfaces, there are three Gigabit Ethernet ports for NTP servers. ...
Timing Receiver: Event Condition Action Unit Figure: A Timing Receiver embedded in a Front End Computer. The core component is the Event Condition Action unit (...
Essentials Figure: Building blocks required for a single 'timing event' Bang!. Components of the General Machine Timing (GMT) are shown in blue. Components requ...
Timing Receiver: Usage For using a Timing Receiver (TR) please follow the directions here. What is Needed * TR hardware, see here what is supported by the cur...
Data Master, UNILAC PZ and Various Gateways An Overview Introduction Today (December 2021) there exist two Machine Timing Systems at GSI. First, the General Ma...
Groups and Machines Figure: Overview on GSI accelerators. Click here for a larger image. Overview Accelerator equipment relevant for the control system is organi...
How To: Gateway Data Master UNILAC Pulszentrale Betrieb Kurzversion * das Gateway ist primitiv * am Gateway kann man nichts einstellen * das Gateway w...
How To: Building and Deployment for Linux Boxes and SCU Most of the code has been developed in the context of the White Rabbit Project and is hosted by the Open H...
How To: White Rabbbit UNILAC PZ (wr unipz) Coding and Deployment Introduction Stack of the White Rabbit Pulszentrale Figure: Overview on the White Rabbit Pu...
How To: Gateway Data Master UNILAC Pulszentrale Konfiguration und Rufbereitschaft Hinweis * Ein How To zur Diagnose der UNILAC Pulszentrale gibt es hier. ...
Data Master: How To Configure and Operate There are different versions of the data master depending on the release of the control system. * Release R12 "Cherr...
Data Master: How To Configure and Operate for Release R1 This describes the temporary solution derived from miniCS (July 2013). This information is outdated, as...
Data Master: How To Configure and Operate for Release R10 ("Pre Cherry") DEPRECATED Introduction This How To is intended for the members of the timing team. The...
Data Master: How To Configure and Operate for Release R11 ("Cherry") Introduction This How To is intended for the members of the timing team. The data master is ...
Data Master: How To Configure and Operate for Release R3 R9 ("Balloon") DEPRECATED Introduction This How To is intended for the members of the timing team. The d...
How To: Command Line Tools for Timing Receiver (including SCU) Introduction A set of command line tools is deployed and available on Front End Computers (FECs). ...
How To: White Rabbit UNILAC PZ (wr unipz) Betrieb Betrieb und Rufbereitschaft Kurzversion * keine Einstellungen fuer Betrieb notwendig * nach SCU Reset ...
How To: Poor Man's (d, m, w) Path to Device Access Introduction This How To is not even a how to. Instead, it is just a collection of stuff required to develop a...
How To: eb fwload Introduction This tool has been written to ease software development form lm32 Soft Cores. It allows to upload firmware to one or more Soft Cor...
How To: eb info Introduction This tool has been written to get information on gateware and firmware actually employed. Usage Usage: eb info OPTION w ...
How To: eb mon Introduction The original intention about this tool has been to get (simpler) access to data of the White Rabbit PTP core. But as the name suggest...
How To: eb rest Introduction This tool has been written to easy 'reset of FPGA'. This cycles the FPGA and (re)loads the image from the flash to the FPGA. Use too...
Timing Messages: How To Snoop the Timing System News FEC for FESA class is now scuxl0143. Introduction This is a first simple solution to view what is going on ...
How To: Check a FEC Introduction This How To describes how to check a FEC works properly with respect to features provided by the GMT. Test Plan This is just a ...
How To: Flash a Timing Receiver with a Gateware/Firmware Image TL;DR * disable all software on the host (FESA, saftd, ...) * SCU only: disable the watchdog...
How To: Installation of a Timing Receiver THIS HOWTO IS DEPRECATED Introduction Installation of a timing receivers should be easy and straight forward. The phy...
Clock Master: How To Operate Introduction This How To is intended for the members of the timing team. The clock master is the White Rabbit Grandmaster Clock of t...
How To: Poor Humans TIF An Ugly Temporary TIF Workaround for the 2021, 2022, 2023 and 2024 Beam Times Introduction As there is currently no replacement for the...
How To: Quick Start THIS HOWTO IS DEPRECATED (look in the /bel_projects readme) The following will provide you with "master" of our our repository. 1 git clo...
How To: saft clk gen Introduction This tool is intended to generate clock trains for fixed frequencies. It uses a simple DDS embedded in the timing receivers gat...
How To: saft ctl Introduction This tool is intended to diagnose the status saftlib and provide ECA related information of a timing receiver. Moreover one can do ...
How To: saft dm Introduction This tool (saft dm: "saft Data Master") is intended to provide a primitive Data Master for local operations in the FEC. This tool mi...
How To: saft io ctl Introduction Use this tool to configure I/Os and setup rules for I/Os in the ECA. Usage IO CTL for SAFTlib Usage: saft io ctl OPTIONS Ar...
How To: saft lcd Introduction This is a an experimental GSI specific command line tool for live display of Beam Production Chains (BPC). Usage via Command Line ...
How To: saft uni Introduction This tool is intended to diagnose UNILAC operation. This tool is experimental! The standard tool saft ctl can of course be used. Ho...
How To: snoopy spy Introduction This is a simple command line tool and provided by one of our colleagues from FEC and available on the ASL 7 cluster. Altho...
How To: LM32 Soft CPU Introduction Soft CPUs are a VDHL implementation of a CPU in a FPGA. With FAIR Timing Receivers, Soft CPUs are directly embedded in the Wis...
How To: LM32 Soft CPU Accessing a LM32 Soft CPU via shared memory and Wishbone Introduction This how to demonstrates how to access the LM32 Soft CPU via Shared...
How To: LM32 Soft CPU Accessing Another SoC Wishbone Device Introduction This how to demonstrates how to access another Wishbone device on the same SoC from th...
How To: LM32 Soft CPU Compiler Introduction This how to describes the status and how to build the compiler for the lm32 soft cpu. Links * on github (for be...
How To: LM32 Soft CPU Send a Command to a LM32 Soft CPU Introduction This how to demonstrates how to send a command to LM32 Soft CPU. This how to demonstrates ...
How To: LM32 Soft CPU Simple Stack Check Introduction This how to demonstrates how a simple check for possible stack violation has been implemented. Principle...
How To: LM32 Soft CPU Using MIL Devicebus Introduction This how to demonstrates how to access a device on a MIL Devicebus connected to the SCU ("MIL piggy"). A...
How To: Installation of a Timing Receiver or SCU THIS HOWTO IS DEPRECATED This how to summarizes the steps required to install a timing receiver. Setup up a FE...
How To: Connecting a Timing Receiver to the White Rabbit Network A timing receiver MUST NOT be connected to a White Rabbit network without authorization. Authori...
HOW TOs This is just a unrevised collection. The purpose is to write down some things, before we forget them... Timing System The recommended official interface ...
Hello World on lm32 Soft CPU THIS HOWTO IS DEPRECATED A soft CPU based on the lm32 is embedded in the White Rabbit core. This how to describes a "Hello World" f...
Installation of Tool Chain for the lm32 Soft CPU THIS HOWTO IS DEPRECATED A soft CPU based on the lm32 is embedded in the White Rabbit core. This how to describ...
Tool Chain for a SPEC Board. THIS HOWTO IS DEPRECATED A soft CPU based on the lm32 is embedded in the White Rabbit core. This how to describes the installation ...
Sending Stuff from GSI Elsewhere THIS HOWTO IS DEPRECATED Requirements * ebiss Account @ GSI, see here * Account number ("Kostenstelle" or "Auftragsnumme...
Timing Messages: How To test the ECA queue from LM32 Soft CPU and PC Introduction The specified ECA queue is used to storage timing events filtered by eventID. T...
How To: Monitoring via Web Pages Introduction This How To describes how to do monitoring via web pages. Access Some web pages are only accessible on the GSI cam...
Building and Deployment for a Specific Kernel and Installation into a Staging Directory THIS HOWTO IS DEPRECATED Remark: This is really special. The information...
Irradiation of Fibres at HHD Cave (SIS18 beam dump) Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be poss...
Irradiation of Fibres at SIS18 Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be possible, that fibres to ...
White Rabbit Switch 802.1X MAC Authentication Introduction This is a standard feature of 'normal' network switches from Cisco, HP, ... and involves a remote Radi...
(Some) Basics of Networking and White Rabbit The prime source for information for White Rabbit project is the Open Hardware Repository. The aim of this page is to...
Release Asterisk v2 (for miniCS) and updates compatible with SaftLib ( OUTDATED ) Asterisk is compatible to the control system releases R3, R4, R5 and R6 The rele...
EXPLODER2C (Release R1) The EXPLODER2C is a carrier board for a stand alone device based on an ArriaII FGPA. It can be White Rabbit enabled using the WREX1 add on...
PEXARIA5 (Release R1) The PEXIARA5A is a PCIe carrier board based on an ArriaV FPGA. It can be White Rabbit enabled using a WREX1 add on board. I/O are implemente...
SCU2 (Release R1) The SCU (Scalable Control Unit) is the standard front end controller used by the CSCO group based on an ArriaII FPGA. It can be White Rabbit ena...
VETAR2 (Release R1) The VETAR2 is a VME carrier board that can be White Rabbit enabled using the VETAR1DB2 add on board. I/Os are defined by a mezzanine board. H...
Snapshot April 2017 DON'T USE THIS SNAPSHOT!!! IT WAS DECIDED TO CANCEL THE ROLL OUT. This snapshot became necessary due to updates of the so called "function...
Snapshot "January 2016" The intention of this snapshot is twofold. First, to make improvement of White Rabbit available at GSI. Second, to provide again a consist...
Introduction to the General Machine Timing System The FAIR facility involves a long chain of accelerators which need to be tightly synchronized. An important cons...
Policies in the Timing Network * The timing network is managed by TOS and TOS defines the policies. * The timing network is a "field bus" synchronizing the...
Releases and Snapshots of the Timing System Release A Timing Firmware Release packs together new features and requirements defined in our Development Road Map, ...
WR Switch: How To Cross Compile DIM THIS HOWTO IS DEPRECATED This describes the first try to cross compile DIM for a White Rabbit switch. DIM is a communication...
WR Switch: How To Flash a WR Switch THIS HOWTO IS DEPRECATED Introduction Most importantly, you should the WRS manual. For version 4.2, see here. Basically, al...
WR Switch: How To Cross Compile Hello World THIS HOWTO IS DEPRECATED This describes how I cross compiled hello world for switch Getting the Tools This assumes ...
WR Switch: How To Use a WR Switch THIS HOWTO IS DEPRECATED This is just a short list of things I found useful Login to a Switch * ssh via the management po...
WR Switch: Basic Remote Monitoring (Deprecated) THIS HOWTO IS DEPRECATED This describes how basic remote monitoring of White Rabbit switches can be done by usin...
How To: TMIS Introduction TMIS (Timing Message Information Service) is a quick evaluation on distribution of timing messages via the ACC controls network. The ma...
White Rabbit Switch Hardware 4.0 Overview This page summarizes the GSI requirements in context with the development of a new version of the White Rabbit Switch. ...
White Rabbbit UNILAC PZ (wr unipz) Introduction UNIPZ Figure: Most simplified view on UNIPZ (upper part). It is a combination of a Super UNIPZ and seven UNI...
General Machine Timing System at GSI and FAIR The FAIR facility involves a long chain of accelerators which need to be tightly synchronized. This is achieved by t...