How-To: saft-clk-gen

Introduction

This tool is intended to generate clock trains for fixed frequencies. It uses a simple DDS embedded in the timing receivers gateware; the DDS uses an input clock of 125 MHz and 32 bits.

Usage

CLK-GEN for SAFTlib
Usage: saft-clk-gen <unique device name> [OPTIONS]

Arguments/[OPTIONS]:
  -n <name>:                                              Specify IO name 
  -p <high phase[ns]> <low phase[ns]> <phase offset[ns]>: Start/Configure clock with the given phases
  -f <frequency[Hz]> <phase offset[ns]>                   Start/Configure clock with the given frequency
  -s:                                                     Stop clock for the given IO
  -i:                                                     List all clock generator outputs
  -v:                                                     Switch to verbose mode
  -h:                                                     Print help (this message)

Example:
saft-clk-gen tr0 -n IO1 -p 4 4 2
  This will generate a 125MHz clock (with a 2ns phase offset)

Report bugs to <csco-tg@gsi.de>
Licensed under the GPLv3

Preparation

Prio starting the clock, please configure the corresponding I/O (click). Example:

saft-io-ctl tr1 -n IO1 -o1 -t0 -d0

-- DietrichBeck - 25 February 2022