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Gateware and Firmware

Gateware and firmware are provided with releases.
  • Gateware: synthesized (V)HDL code
  • Firmware: compiled code for the lm32 soft-CPU embedded in the gateware

Wishbone Bus Topology

The following figure shows the topology of the Enigma release.

monster.png
Figure: Wishbone Bus Topology (see 'Attachments' for higher resolution). Shown are Wishbone crossbars (yellow ovals), masters (green diamonds) and slaves (gray rectangles). Arrows show Wishbone connections to slaves (black) and crossbar interconnects (red). MSI connections are shown in blue arrows.

I/O Connections

The following figures shows how I/Os are connected to various gateware components (~ Enigma release)

io-gates.jpg
Figure: I/O connections.

-- DietrichBeck - 30 Sep 2020
I Attachment Action Size Date Who Comment
SCU_Layout2_landscape.jpgjpg SCU_Layout2_landscape.jpg manage 238 K 28 Nov 2013 - 13:50 DietrichBeck Data Master WB Layout
io-gates.jpgjpg io-gates.jpg manage 537 K 30 Sep 2020 - 09:54 DietrichBeck IO connections
monster.pngpng monster.png manage 485 K 30 Sep 2020 - 09:44 DietrichBeck Wishbone Topology
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Topic revision: r8 - 30 Sep 2020, DietrichBeck
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