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TimingSystemDocumentsAddOnBoardFeatures

Feature List for Add On boards of Timing Receivers at GSI and FAIR This page lists some hardware features for add on boards. Such add on boards are mezzanine boar...

r11 - 01 Nov 2013 - 08:15 by DietrichBeck

TimingSystemDocumentsBlackCat1

Black_Cat1 Mezzanine Board The Black Cat mezzanine board extends the PEXARIA5 board with I/Os. However, the WR1 connector on Black Cat is no longer used, as the W...

r4 - 15 Jul 2014 - 14:50 by DietrichBeck

TimingSystemDocumentsConnectionEELabor

Connection to EE Labor This is just a temporary document, to be replaced by some proper documentation. Note on calculating cable lengths The cable length has bee...

r6 - 22 Apr 2024 - 05:40 by DietrichBeck

TimingSystemDocumentsFTRNFeatures

Feature List for Timing Receivers at GSI and FAIR This page lists some hardware features for timing receivers at GSI and FAIR. Some recommended features will beco...

r13 - 25 Sep 2014 - 20:07 by DietrichBeck

TimingSystemDocumentsGateFirmWare

Gateware and Firmware Gateware and firmware are provided with releases. * Gateware: synthesized (V)HDL code * Firmware: compiled code for the lm32 soft CPU ...

r8 - 30 Sep 2020 - 09:59 by DietrichBeck

TimingSystemDocumentsMaster

The FAIR Timing Master in the "Betriebsgebäude" BG This is a collection of documents related to the FAIR Timing Master in the "Elektronikraum". Equipment Rack5...

r10 - 29 Oct 2019 - 12:44 by DietrichBeck

TimingSystemDocumentsNetwork

Timing Network Networks There are several instances of timing networks on the campus. * Productive * production: everything starting with the end of TK ...

r3 - 22 Apr 2024 - 05:42 by DietrichBeck

TimingSystemDocumentsPEXARIA5DB1

PEXARIA5DB The PEXIARA5DB is a mezzanine card for a PEXARIA5 carrier board. It exists in two variants. * PEXARIA5DB1, with IDC connector for LVDS signals: sche...

r4 - 05 May 2014 - 07:33 by DietrichBeck

TimingSystemDocumentsRep201607222

Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...

r6 - 30 Jan 2018 - 09:55 by DietrichBeck

TimingSystemDocumentsRep20211222

Booster Test December 2021 TL;DR For 'booster mode': * timing the beam transfer from UNILAC to SIS18 works with ~98% efficiency, if rf conditioning at UNILAC ...

r6 - 13 Jan 2022 - 09:04 by DietrichBeck

TimingSystemDocumentsReportsAndMeasurements

Reports and Measurements This page serves to collect reports and measurements on the GMT. Booster Test * Timing events during 1st Booster Mode Test (2021 12 1...

r37 - 22 Apr 2024 - 05:44 by DietrichBeck

TimingSystemDocumentsSIXIO2

FMC Module SIXIO2 The FMC module SIXIO2 has been designed by Jan Hoffmann / EE. It's purpose is simple I/O. * Info by EE: Some figures and specs * Sixio2_SC...

r5 - 15 Jul 2014 - 12:57 by DietrichBeck

TimingSystemDocumentsSaftlib

Simple API For Timing (SaftLib) Simple API For Timing (SAFT). The design and implementation of SaftLib is a major project. Introduction The key features SaftLib ...

r35 - 28 Aug 2023 - 13:32 by DietrichBeck

TimingSystemDoomsdayRelease

Doomsday Release (DEPRECATED) Previous releases are Asterisk, Balloon and Cherry. This release is replaced by Enigma. New features and bug fixes in Doomsday Rel...

r20 - 14 Nov 2019 - 15:23 by DietrichBeck

TimingSystemEBWireshark

How To: Etherbone with Wireshark Introduction Wireshark might be useful when you need to inspect Etherbone packages sent via Ethernet, see here. Here are a few h...

r3 - 11 Oct 2019 - 13:41 by DietrichBeck

TimingSystemERelease

Enigma Release (DEPRECATED) Previous releases are Asterisk, Balloon, Cherry and Doomsday. This release has been replaced by release Fallout. New Features and Bu...

r36 - 01 Oct 2020 - 14:45 by DietrichBeck

TimingSystemErrorMsg

Documentation of Data Master Error Messages Parser Errors caused by faulty schedule data If any of the following error messages are reported to you or appear in ...

NEW - 17 Feb 2021 - 13:55 by MathiasKreider

TimingSystemEtherbone

Etherbone Introduction The idea behind the EtherBone (EB) protocol is to extend the reach of the embedded Wishbone (WB) V4 System on a chip (SoC) bus system to r...

r4 - 08 Oct 2022 - 21:02 by DietrichBeck

TimingSystemEvent

Timing Messages Format of a Timing Message Timing messages is a term describing the input to a Timing Receiver (TR) that possibly leads to generation of a so cal...

r34 - 18 Aug 2020 - 15:47 by DietrichBeck

TimingSystemEventNumbers

Event Numbers Overview Event numbers serve as IDs for actions performed by the control system. Existing Facility Information about event numbers used by the ex...

r33 - 24 Jan 2024 - 11:05 by DietrichBeck

TimingSystemFEC

How To: WB_FEC This wiki provides information about * WB FEC VHDL module and integration in Bel_Projects * Synthesis of Timing Receiver Gateware with the WB...

r14 - 05 Apr 2018 - 07:16 by DietrichBeck

TimingSystemFRelease

Fallout Release Previous releases are Asterisk, Balloon, Cherry, Doomsday and Enigma New features and bug fixes in Fallout Release * 2020 Aug 31: v6.0.0 alph...

r56 - 26 Apr 2023 - 15:27 by DietrichBeck

TimingSystemFrontendAccess

How To: Accessing ACO Frontends Using ACO Tools Introduction This how to is just intended as a primer for non specialists. Disclaimer: There are many, many possi...

r5 - 23 Mar 2022 - 10:39 by DietrichBeck

TimingSystemGPSDO

GPSDO The GPSDO serves as a primary reference time source for the timing system. Amongst the interfaces, there are three Gigabit Ethernet ports for NTP servers. ...

r9 - 13 Nov 2017 - 13:26 by DietrichBeck

TimingSystemGSEca

Timing Receiver: Event Condition Action Unit Figure: A Timing Receiver embedded in a Front End Computer. The core component is the Event Condition Action unit (...

r6 - 16 Nov 2018 - 11:01 by DietrichBeck

TimingSystemGSOverview

Essentials Figure: Building blocks required for a single 'timing event' Bang!. Components of the General Machine Timing (GMT) are shown in blue. Components requ...

r4 - 13 Nov 2018 - 09:04 by DietrichBeck

TimingSystemGSTrUsage

Timing Receiver: Usage For using a Timing Receiver (TR) please follow the directions here. What is Needed * TR hardware, see here what is supported by the cur...

r5 - 10 Feb 2020 - 17:02 by DietrichBeck

TimingSystemGettingStarted

Getting Started * Essentials * Timing Receiver: Event Condition Action Unit * Timing Receiver: Usage Main.DietrichBeck 16 Nov 2018

r5 - 16 Nov 2018 - 09:47 by DietrichBeck

TimingSystemGmtUnipz

Data Master, UNILAC PZ and Various Gateways An Overview Introduction Today (December 2021) there exist two Machine Timing Systems at GSI. First, the General Ma...

r3 - 08 Dec 2021 - 15:03 by DietrichBeck

TimingSystemGroupsAndMachines

Groups and Machines Figure: Overview on GSI accelerators. Click here for a larger image. Overview Accelerator equipment relevant for the control system is organi...

r53 - 22 Aug 2023 - 12:55 by DietrichBeck

TimingSystemHowBasicsDMUniPZ

Einleitung Das Gateway hat die Aufgabe, das zeitbasierte White Rabbit Timingsystem mit der eventbasierten UNILAC Pulszentrale (UNIPZ) zu verbinden. Bei UNIPZ wurd...

r2 - 24 Apr 2024 - 07:37 by DietrichBeck

TimingSystemHowBetriebDMUniPZ

How To: Gateway Data Master UNILAC Pulszentrale Betrieb Kurzversion * das Gateway ist primitiv * am Gateway kann man nichts einstellen * das Gateway w...

NEW - 18 Nov 2021 - 18:04 by DietrichBeck

TimingSystemHowBuildingDeployment

How To: Building and Deployment for Linux Boxes and SCU Most of the code has been developed in the context of the White Rabbit Project and is hosted by the Open H...

r77 - 11 May 2023 - 06:23 by DietrichBeck

TimingSystemHowCodeDeployWRUniPZ

How To: White Rabbbit UNILAC PZ (wr unipz) Coding and Deployment Introduction Stack of the White Rabbit Pulszentrale Figure: Overview on the White Rabbit Pu...

r7 - 17 Nov 2021 - 11:12 by DietrichBeck

TimingSystemHowConfigureDMUniPZ

How To: Gateway Data Master UNILAC Pulszentrale Konfiguration und Rufbereitschaft Hinweis * Ein How To zur Diagnose der UNILAC Pulszentrale gibt es hier. ...

r51 - 24 Apr 2024 - 05:42 by DietrichBeck

TimingSystemHowConfigureDataMaster

Data Master: How To Configure and Operate There are different versions of the data master depending on the release of the control system. * Release R12 "Cherr...

r9 - 12 Mar 2018 - 09:57 by MathiasKreider

TimingSystemHowConfigureDataMasterR1

Data Master: How To Configure and Operate for Release R1 This describes the temporary solution derived from miniCS (July 2013). This information is outdated, as...

r3 - 10 Jul 2014 - 08:42 by DietrichBeck

TimingSystemHowConfigureDataMasterR10

Data Master: How To Configure and Operate for Release R10 ("Pre Cherry") DEPRECATED Introduction This How To is intended for the members of the timing team. The...

r3 - 04 Dec 2017 - 07:51 by DietrichBeck

TimingSystemHowConfigureDataMasterR11

Data Master: How To Configure and Operate for Release R11 ("Cherry") Introduction This How To is intended for the members of the timing team. The data master is ...

r2 - 08 Dec 2017 - 08:15 by DietrichBeck

TimingSystemHowConfigureDataMasterR3

Data Master: How To Configure and Operate for Release R3 R9 ("Balloon") DEPRECATED Introduction This How To is intended for the members of the timing team. The d...

r14 - 04 Dec 2017 - 07:52 by DietrichBeck

TimingSystemHowConfigureEnvironment

Ohps! You are looking for an old wiki page that has been renamed. Try this wiki page Main.DietrichBeck 19 Jun 2019

NEW - 19 Jun 2019 - 13:58 by DietrichBeck

TimingSystemHowConfigureFTRNCommandLine

How To: Command Line Tools for Timing Receiver (including SCU) Introduction A set of command line tools is deployed and available on Front End Computers (FECs). ...

r25 - 25 Feb 2022 - 11:45 by DietrichBeck

TimingSystemHowConfigureFTRNVME

FAIR Timing Receiver Node: How To Configure and Operate a VME Timing Receiver (outdated) THIS HOWTO IS DEPRECATED August 2013 Introduction The VETAR2 is the ne...

r7 - 19 Jun 2019 - 13:35 by DietrichBeck

TimingSystemHowConfigureWRMILGW

WR MIL gateway Introduction WR MIL gateways are a replacement for the existing SIS and ESR Pulszentrale (PZ). They are implemented in software running on a LM32 s...

r27 - 08 Jun 2021 - 10:00 by MichaelReese

TimingSystemHowConfigureWRUniPZ

How To: White Rabbit UNILAC PZ (wr unipz) Betrieb Betrieb und Rufbereitschaft Kurzversion * keine Einstellungen fuer Betrieb notwendig * nach SCU Reset ...

r16 - 18 Nov 2021 - 17:11 by DietrichBeck

TimingSystemHowDMUniPZ

Gateway Data Master UNILAC Pulszentrale (DM UNIPZ) DM UNIPZ * Betrieb * Configuration and Rufbereitschaft * (for editing the basics, click) Further...

NEW - 18 Nov 2021 - 17:37 by DietrichBeck

TimingSystemHowDebugSaftlibWithGDB

Remote debugging of a running saft daemon with GDB It is possible to connect GDB to a running SCU, set breakpoints, step through the code, print variables, etc. T...

r2 - 13 Oct 2021 - 12:19 by MichaelReese

TimingSystemHowDevAcc

How To: Poor Man's (d, m, w) Path to Device Access Introduction This How To is not even a how to. Instead, it is just a collection of stuff required to develop a...

r14 - 31 Aug 2020 - 09:57 by DietrichBeck

TimingSystemHowEbFwload

How To: eb fwload Introduction This tool has been written to ease software development form lm32 Soft Cores. It allows to upload firmware to one or more Soft Cor...

r4 - 19 Jun 2019 - 13:55 by DietrichBeck

TimingSystemHowEbInfo

How To: eb info Introduction This tool has been written to get information on gateware and firmware actually employed. Usage Usage: eb info OPTION w ...

r2 - 19 Jun 2019 - 12:11 by DietrichBeck

Number of topics: 50

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