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You are here: Foswiki>Timing Web>WebChanges (09 Jan 2009, ProjectContributor)Edit Attach
50 recent changes in Timing Web retrieved at 07:10 (GMT)
TimingSystemDocumentRep20180904
SCU Kernel Task Switching Latency Introduction The hardware group (thx to Stefan!) has investigated task switchting / preemption on the SCU kernel with RT patch ...
r6 - 27 Sep 2018 - 14:40 by DietrichBeck
TimingSystemFEC
How To: WB_FEC This wiki provides information about * WB FEC VHDL module and integration in Bel_Projects * Synthesis of Timing Receiver Gateware with the WB...
r14 - 05 Apr 2018 - 07:16 by DietrichBeck
TimingSystemHowConfigureDataMaster
Data Master: How To Configure and Operate There are different versions of the data master depending on the release of the control system. * Release R12 "Cherr...
r9 - 12 Mar 2018 - 09:57 by MathiasKreider
TimingSystemNextReleaseCandidate
"D?" Candidate Release Probably in March 2018. See here. Main.DietrichBeck 01 Mar 2018
r3 - 01 Mar 2018 - 11:15 by DietrichBeck
TimingSystemDocumentsRep201607222
Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...
r6 - 30 Jan 2018 - 09:55 by DietrichBeck
WRSimulation
WR Simulation How To This How To guide you in the simulation of the WR Core and WR Switch. Setup the Simulation environment You need a ModelSim runnig in your sy...
r5 - 24 Jan 2018 - 15:40 by cprados
TimingSystemHowOperateClockMaster
Clock Master: How To Operate Introduction This How To is intended for the members of the timing team. The clock master is the White Rabbit Grandmaster Clock of t...
r4 - 23 Dec 2017 - 09:27 by DietrichBeck
TimingSystemHowConfigureDataMasterR11
Data Master: How To Configure and Operate for Release R11 ("Cherry") Introduction This How To is intended for the members of the timing team. The data master is ...
r2 - 08 Dec 2017 - 08:15 by DietrichBeck
TimingSystemNodesReleaseAsteriskPexaria5Commission
Step by step guide to commissioning a new pexaria5: 1 Place powered off pexaria5 on ESD desk , ESD dischare! 1 Attach wrex2a addon board to baseboard WR1 (W...
r20 - 05 Dec 2017 - 10:33 by DietrichBeck
TimingSystemHowConfigureDataMasterR3
Data Master: How To Configure and Operate for Release R3 R9 ("Balloon") DEPRECATED Introduction This How To is intended for the members of the timing team. The d...
r14 - 04 Dec 2017 - 07:52 by DietrichBeck
TimingSystemHowConfigureDataMasterR10
Data Master: How To Configure and Operate for Release R10 ("Pre Cherry") DEPRECATED Introduction This How To is intended for the members of the timing team. The...
r3 - 04 Dec 2017 - 07:51 by DietrichBeck
SaftlibEtherboneLm32LatencyMeasurement
MSI/IRQ Latency Measurements with LM32, Etherbone and Saftlib In autumn 2017, the latency of Message Signalled Interrupts (MSI) has been measured involving differ...
r5 - 30 Nov 2017 - 14:24 by MichaelReese
Wrlldp
How To: WR LLDP This how to describes how to use LLDP in WR Devices. It is not meant to clarify what is LLDP. Info (November 2017): The development is already in...
r4 - 15 Nov 2017 - 09:38 by DietrichBeck
TimingSystemGPSDO
GPSDO The GPSDO serves as a primary reference time source for the timing system. Amongst the interfaces, there are three Gigabit Ethernet ports for NTP servers. ...
r9 - 13 Nov 2017 - 13:26 by DietrichBeck
TimingSystemDBusInfo
Main.MichaelReese 30 Sep 2016 Saftlib is constructed around the DBus IPC system. In order to maintain and develop the library, a fairly good understanding of the ...
r16 - 15 Sep 2017 - 09:10 by MichaelReese
TimingSystemNodesSnapshotApr2017
Snapshot April 2017 DON'T USE THIS SNAPSHOT!!! IT WAS DECIDED TO CANCEL THE ROLL OUT. This snapshot became necessary due to updates of the so called "function...
r5 - 05 May 2017 - 07:18 by DietrichBeck
TimingSystemHowSoftCPULM32Command
How To: LM32 Soft CPU Send a Command to a LM32 Soft CPU Introduction This how to demonstrates how to send a command to LM32 Soft CPU. This how to demonstrates ...
r2 - 28 Mar 2017 - 08:50 by DietrichBeck
TimingSystemHowSoftCPUUseDevicebus
How To: LM32 Soft CPU Using MIL Devicebus Introduction This how to demonstrates how to access a device on a MIL Devicebus connected to the SCU ("MIL piggy"). A...
r2 - 28 Mar 2017 - 08:49 by DietrichBeck
TimingSystemHowSoftCPUAccessLM32SharedMemWB
How To: LM32 Soft CPU Accessing a LM32 Soft CPU via shared memory and Wishbone Introduction This how to demonstrates how to access the LM32 Soft CPU via Shared...
r2 - 28 Mar 2017 - 08:48 by DietrichBeck
TimingSystemHowSoftCPUAccessOtherWB
How To: LM32 Soft CPU Accessing Another SoC Wishbone Device Introduction This how to demonstrates how to access another Wishbone device on the same SoC from th...
r2 - 28 Mar 2017 - 08:47 by DietrichBeck
EXPLODER5A
Figure 1: A complete exploder5a module (top view). Main.AlexanderHahn 15 Jul 2015
r2 - 23 Feb 2016 - 15:03 by DietrichBeck
TimingSystemNodesReleaseAsteriskVetar2aCommission
Vetar2a Commissioning Guide Note: This test is functional. It is not intended to cover verification validation tests of the design! Needed components for each...
r11 - 22 Oct 2015 - 14:44 by AlexanderHahn
FirmwareID
Main.MathiasKreider 07 May 2015 Getting Information about the Firmware on a device Firmware IDs The eb info tool was used to read out the build id ROM, providin...
r3 - 11 May 2015 - 09:06 by MathiasKreider
TimingSystemNodesReleaseR1VETAR2
VETAR2 (Release R1) The VETAR2 is a VME carrier board that can be White Rabbit enabled using the VETAR1DB2 add on board. I/Os are defined by a mezzanine board. H...
r22 - 06 Nov 2014 - 16:39 by DietrichBeck
TimingSystemLSAInterface
FESA Properties for DataMaster Class (current version running on vmla03) Global Interface (Device Name MCS_DM_GLOBAL) Setting Properties * Command * dataM...
r10 - 22 Oct 2014 - 09:37 by MathiasKreider
TimingSystemDataMasterXMLFormat
The XML Format Used by the Data Master The DM uses an XML format to describe a schedule. Presently (09/2014), this format depends on implementation details. A (no...
NEW - 29 Sep 2014 - 11:54 by DietrichBeck
TimingSystemDocumentsFTRNFeatures
Feature List for Timing Receivers at GSI and FAIR This page lists some hardware features for timing receivers at GSI and FAIR. Some recommended features will beco...
r13 - 25 Sep 2014 - 20:07 by DietrichBeck
TimingSystemNodesReleaseR1Exploder2C
EXPLODER2C (Release R1) The EXPLODER2C is a carrier board for a stand alone device based on an ArriaII FGPA. It can be White Rabbit enabled using the WREX1 add on...
r14 - 17 Jul 2014 - 08:24 by DietrichBeck
TimingSystemNodesReleaseR1
Nodes: Release R1 Overview rpd ...
NEW - 15 Jul 2014 - 15:04 by DietrichBeck
TimingSystemNodesReleaseR1SCU2
SCU2 (Release R1) The SCU (Scalable Control Unit) is the standard front end controller used by the CSCO group based on an ArriaII FPGA. It can be White Rabbit ena...
r3 - 15 Jul 2014 - 14:56 by DietrichBeck
TimingSystemNodesReleaseR1PEXARIA5
PEXARIA5 (Release R1) The PEXIARA5A is a PCIe carrier board based on an ArriaV FPGA. It can be White Rabbit enabled using a WREX1 add on board. I/O are implemente...
r16 - 15 Jul 2014 - 14:52 by DietrichBeck
TimingSystemDocumentsBlackCat1
Black_Cat1 Mezzanine Board The Black Cat mezzanine board extends the PEXARIA5 board with I/Os. However, the WR1 connector on Black Cat is no longer used, as the W...
r4 - 15 Jul 2014 - 14:50 by DietrichBeck
TimingSystemDocumentsSIXIO2
FMC Module SIXIO2 The FMC module SIXIO2 has been designed by Jan Hoffmann / EE. It's purpose is simple I/O. * Info by EE: Some figures and specs * Sixio2_SC...
r5 - 15 Jul 2014 - 12:57 by DietrichBeck
TimingSystemBuTiSReceiver
BuTiS Receiver Station The BuTiS receiver station are maintained by the RF group, contact persons are P. Moritz or B. Zipfel. Setup Figure 1: BuTiS receiver sta...
r9 - 15 Jul 2014 - 11:12 by DietrichBeck
TimingSystemManagementMaster
Management Master Configuration ... to be done... Main.DietrichBeck 03 Apr 2014
r2 - 15 Jul 2014 - 11:12 by DietrichBeck
TimingSystemHowConfigureDataMasterR1
Data Master: How To Configure and Operate for Release R1 This describes the temporary solution derived from miniCS (July 2013). This information is outdated, as...
r3 - 10 Jul 2014 - 08:42 by DietrichBeck
TimingSystemDocumentsPEXARIA5DB1
PEXARIA5DB The PEXIARA5DB is a mezzanine card for a PEXARIA5 carrier board. It exists in two variants. * PEXARIA5DB1, with IDC connector for LVDS signals: sche...
r4 - 05 May 2014 - 07:33 by DietrichBeck
TimingSystemDocumentsAddOnBoardFeatures
Feature List for Add On boards of Timing Receivers at GSI and FAIR This page lists some hardware features for add on boards. Such add on boards are mezzanine boar...
r11 - 01 Nov 2013 - 08:15 by DietrichBeck
WebPreferences
Timing Web Preferences Appearance * Set WEBBGCOLOR = #669966 * web specific background color, current color * Set SITEMAPLIST = on * set to...
GSITimingTeam
FAIR Timing/GSI Timing Team Core members of the GSI Timing Team are: T.Fleck C.Prados S.Rauch M.Kreider Further leading actors within the GSI controls group are U...
r3 - 05 Mar 2009 - 07:55 by TiborFleck
NetworkTopologyInterfaces
* chap2.pdf: Chapter2 Topology Main.CesarPrados 03 Mar 2009
r2 - 04 Mar 2009 - 13:52 by TiborFleck
WebAtom
Foswiki's Timing web
NEW - 09 Jan 2009 - 12:00 by ProjectContributor
WebRss
" else="Foswiki's Timing web"}% /Timing
NEW - 09 Jan 2009 - 12:00 by ProjectContributor
WebLeftBar
" warn="off"}% * ** * * * * * * * *
NEW - 09 May 2007 - 21:29 by ProjectContributor
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