General Machine Timing System at GSI and FAIR The FAIR facility involves a long chain of accelerators which need to be tightly synchronized. This is achieved by t...
Data Master Manuals DM Technote: DM Manual. A DM Firmware and API Documentation. WIP, about 80% complete. Still trying to keep up with all the implemented feature...
How to run and develop tests for the Datamaster Run Tests with pytest The folder modules/ftm/tests has a Makefile. The important targets are: all, remote, prepar...
HOW TOs This is just a unrevised collection. The purpose is to write down some things, before we forget them... Timing System The recommended official interface ...
Description of the features for the UNILAC Datamaster This describes the planned features for the UNILAC datamaster. The features were presented at the Workshop U...
Reports and Measurements This page serves to collect reports and measurements on the GMT. Booster Test * Timing events during 1st Booster Mode Test (2021 12 1...
Event Numbers Overview Event numbers serve as IDs for actions performed by the control system. Existing Facility Information about event numbers used by the ex...
How To: Monitoring via Web Pages Introduction This How To describes how to do monitoring via web pages. Access Some web pages are only accessible on the GSI cam...
Documentation Data Master Test System Hardware SuperMicro fel0069 The data master for the test system is hosted on SuperMicro fel0069 with two PEXARIA5d (fel006...
How To: Check a FEC Introduction This How To describes how to check a FEC works properly with respect to features provided by the GMT. Test Plan This is just a ...
How To: saft uni Introduction This tool is intended to diagnose UNILAC operation. This tool is experimental! The standard tool saft ctl can of course be used. Ho...
Simple API For Timing (SaftLib) Simple API For Timing (SAFT). The design and implementation of SaftLib is a major project. Introduction The key features SaftLib ...
Groups and Machines Figure: Overview on GSI accelerators. Click here for a larger image. Overview Accelerator equipment relevant for the control system is organi...
Main.MichaelReese 14 Aug 2023 Device Driver Tutorial EB slave WB master over PCIe The goal is to write an Etherbone slave that controls a wishbone master on the ...
How To: Gateway Data Master UNILAC Pulszentrale Konfiguration und Rufbereitschaft Hinweis * Ein How To zur Diagnose der UNILAC Pulszentrale gibt es hier. ...
Main.MichaelReese 15 Feb 2018 PCIe WB bridge direct access mode PCIe timing hardware where the PCIe bridge has been modified to support the "direct access mode" ...
How To: Building and Deployment for Linux Boxes and SCU Most of the code has been developed in the context of the White Rabbit Project and is hosted by the Open H...
Fallout Release Previous releases are Asterisk, Balloon, Cherry, Doomsday and Enigma New features and bug fixes in Fallout Release * 2020 Aug 31: v6.0.0 alph...
HOW TO: Use xdot to analyze schedules Based on Graphviz dot language there is the tool xdot. A GSI fork of xdot (one of 136 forks) enhances this to analyze schedu...
"wr unipz" is a component of the MIL based UNILAC 'Pulszentrale' (UNIPZ). As a field bus, it does not use the MIL 'Event' bus but a White Rabbit network. Logicall...
Run the ordinary and boundary clocks using linuxptp The linuxptp package is a PTPv2 implementation according to the IEEE 1588 standard for Linux. It includes the ...
How To: eb rest Introduction This tool has been written to easy 'reset of FPGA'. This cycles the FPGA and (re)loads the image from the flash to the FPGA. Use too...
Test the interoperability of the IEEE 1588 capable network adapters with the White Rabbit switches Introduction This report presents the interoperability between...
GHDL coupling to C via VHPI Motivation It is often useful to call into c libraries from within a VHDL simulation/testbench * because VHDL standard library is ...
Etherbone Introduction The idea behind the EtherBone (EB) protocol is to extend the reach of the embedded Wishbone (WB) V4 System on a chip (SoC) bus system to r...
Install etherbone library on tsl101 server * login on acc8 dev cluster (e.g. asl751) and clone repo and checkout correct branch git clone https://github.com/GS...
Synchronize the clock of non WR devices in the WR network 1. Introduction This document presents specific configurations of White Rabbit (WR) switches, which are...
WR PTP synchronization of WRS under excessive PTP and LLDP traffic 1. Introduction The White Rabbit (WR) technique is specially developed to provide sub nanose...
How To: eb console Set a static IP Timing receivers not connected to a bootp server require a static IP for full operation. This is to be set via the eb console ...
Use port mirroring on a WR switch (WRS) 1. Introduction Although port mirroring is supported by WRSs a corresponding command option is not documented in the user...
How To: Accessing ACO Frontends Using ACO Tools Introduction This how to is just intended as a primer for non specialists. Disclaimer: There are many, many possi...
Authentication of network nodes and assginment of virtual LAN using the White Rabbit switches 1. Introduction The 802.1x authentication standard is supported by ...
How To: saft clk gen Introduction This tool is intended to generate clock trains for fixed frequencies. It uses a simple DDS embedded in the timing receivers gat...
How To: Command Line Tools for Timing Receiver (including SCU) Introduction A set of command line tools is deployed and available on Front End Computers (FECs). ...
Gateway Data Master UNILAC PZ (dm unipz) Introduction "dm unipz" is the interface between the White Rabbit based Data Master und the MIL based UNILAC 'Pulszentr...
Deprecated HOW TOs This is just a unrevised collection of outdated or deprecated HOW TOs. Timing Receivers * Building and Installation * HOW TO: Instal...
Booster Test December 2021 TL;DR For 'booster mode': * timing the beam transfer from UNILAC to SIS18 works with ~98% efficiency, if rf conditioning at UNILAC ...
Booster Test November 2021 Introduction The so called 'Booster Mode' shall be used to accumulate beam from multiple SIS18 injections into SIS100 at a rate of abo...
White Rabbit Switch 802.1X MAC Authentication Introduction This is a standard feature of 'normal' network switches from Cisco, HP, ... and involves a remote Radi...
Data Master, UNILAC PZ and Various Gateways An Overview Introduction Today (December 2021) there exist two Machine Timing Systems at GSI. First, the General Ma...
Einleitung Das Gateway hat die Aufgabe, das zeitbasierte White Rabbit Timingsystem mit der eventbasierten UNILAC Pulszentrale (UNIPZ) zu verbinden. Bei UNIPZ wurd...
How To: Gateway Data Master UNILAC Pulszentrale Betrieb Kurzversion * das Gateway ist primitiv * am Gateway kann man nichts einstellen * das Gateway w...
How To: White Rabbit UNILAC PZ (wr unipz) Betrieb Betrieb und Rufbereitschaft Kurzversion * keine Einstellungen fuer Betrieb notwendig * nach SCU Reset ...
White Rabbbit UNILAC PZ (wr unipz) Introduction UNIPZ Figure: Most simplified view on UNIPZ (upper part). It is a combination of a Super UNIPZ and seven UNI...
How To: White Rabbbit UNILAC PZ (wr unipz) Coding and Deployment Introduction Stack of the White Rabbit Pulszentrale Figure: Overview on the White Rabbit Pu...
How To: Flash a Timing Receiver with a Gateware/Firmware Image TL;DR * disable all software on the host (FESA, saftd, ...) * SCU only: disable the watchdog...
Remote debugging of a running saft daemon with GDB It is possible to connect GDB to a running SCU, set breakpoints, step through the code, print variables, etc. T...
Monitor local system time of a WRS via SNMP 1. Introduction WRS synchronises its local time with an external NTP server, if one is specified in CONFIG_NTP_SERVER...
WR MIL gateway Introduction WR MIL gateways are a replacement for the existing SIS and ESR Pulszentrale (PZ). They are implemented in software running on a LM32 s...
How To: Poor Humans TIF An Ugly Temporary TIF Workaround for the 2021 Beam Time Introduction As there is currently no replacement for the MIL TIFs with the new...
PEXP Testing and Commissioning Guide Attention: This guide does not check the whole PCIe standard! Attention: This is NOT for FAT Required component...
Saftlib Latency Measurements During the startup of the accelerator in February 2021, issues have been observed with the so called function generator (FG): Occasio...
Reading the DM status To get an overview on whats running on a DM, you can get the basic status by issuing root@tsl017 ~ # dm cmd dev/wbm0 or root@tsl017 ~ # dm...
Documentation of Data Master Error Messages Parser Errors caused by faulty schedule data If any of the following error messages are reported to you or appear in ...
Sending Stuff from GSI Elsewhere THIS HOWTO IS DEPRECATED Requirements * ebiss Account @ GSI, see here * Account number ("Kostenstelle" or "Auftragsnumme...
How To: TMIS Introduction TMIS (Timing Message Information Service) is a quick evaluation on distribution of timing messages via the ACC controls network. The ma...
GSI Timing Team Core members of the GSI Timing Team are: F. Ameil (associated): work package lead (FAIR) D. Beck: operation, tools and docs, legacy stuff for UNIL...
Timing Messages: How To Snoop the Timing System News FEC for FESA class is now scuxl0143. Introduction This is a first simple solution to view what is going on ...
How To: Configuring and using Altera Ethernet Blaster to flash DM PRO * Download current gateware archive, unpack * Copy jic file to tmp directory on tsl021...
How To: Setting Up a Linux Box Intended usage: E Release For older releases please check out the history of this Wiki page. Introduction This how to describes se...
How To: saft ctl Introduction This tool is intended to diagnose the status saftlib and provide ECA related information of a timing receiver. Moreover one can do ...
How To: saft dm Introduction This tool (saft dm: "saft Data Master") is intended to provide a primitive Data Master for local operations in the FEC. This tool mi...
White Rabbit, BuTiS, Clocks and Time Introduction Two systems exist for distribution of time stamps and clocks: 1. The General Machine Timing System provides ...
Testing and Commissioning Guide for Pexaria5 Required components * Pexaria5 under test (named as P5UT in this guide) * PC with Intel Quartus (version 18...
Enigma Release (DEPRECATED) Previous releases are Asterisk, Balloon, Cherry and Doomsday. This release has been replaced by release Fallout. New Features and Bu...
Gateware and Firmware Gateware and firmware are provided with releases. * Gateware: synthesized (V)HDL code * Firmware: compiled code for the lm32 soft CPU ...
Releases and Snapshots of the Timing System Release A Timing Firmware Release packs together new features and requirements defined in our Development Road Map, ...
How To: saft io ctl Introduction Use this tool to configure I/Os and setup rules for I/Os in the ECA. Usage IO CTL for SAFTlib Usage: saft io ctl OPTIONS Ar...
How To: Connecting a Timing Receiver to the White Rabbit Network A timing receiver MUST NOT be connected to a White Rabbit network without authorization. Authori...
How To: LM32 Soft CPU Compiler Introduction This how to describes the status and how to build the compiler for the lm32 soft cpu. Links * on github (for be...
How To: Poor Man's (d, m, w) Path to Device Access Introduction This How To is not even a how to. Instead, it is just a collection of stuff required to develop a...
Timing Messages Format of a Timing Message Timing messages is a term describing the input to a Timing Receiver (TR) that possibly leads to generation of a so cal...
White Rabbit Switch Hardware 4.0 Overview This page summarizes the GSI requirements in context with the development of a new version of the White Rabbit Switch. ...
How To: saft lcd Introduction This is a an experimental GSI specific command line tool for live display of Beam Production Chains (BPC). Usage via Command Line ...
Timing Receiver: Usage For using a Timing Receiver (TR) please follow the directions here. What is Needed * TR hardware, see here what is supported by the cur...
(Some) Basics of Networking and White Rabbit The prime source for information for White Rabbit project is the Open Hardware Repository. The aim of this page is to...
How To: LM32 Soft CPU Introduction Soft CPUs are a VDHL implementation of a CPU in a FPGA. With FAIR Timing Receivers, Soft CPUs are directly embedded in the Wis...
Report: Latency and Loss of Timing Messages in the Timing System Introduction Starting in October 2019 the ECA Tap module was added to the gateware of a few dedi...
AMC Testing and Commissioning Guide Required components for each uTCA device * SFP (green/purple) * LC cable and a white rabbit switch (Recommended: RUN...
How To: Quick Start THIS HOWTO IS DEPRECATED (look in the /bel_projects readme) The following will provide you with "master" of our our repository. 1 git clo...
Policies in the Timing Network * The timing network is managed by TOS and TOS defines the policies. * The timing network is a "field bus" synchronizing the...
Doomsday Release (DEPRECATED) Previous releases are Asterisk, Balloon and Cherry. This release is replaced by Enigma. New features and bug fixes in Doomsday Rel...
Main.MichaelReese 07 Feb 2019 In response to user requests for lower latency communication and fewer library dependencies in saftlib, API breaking changes are int...
Installing Quartus 18.1 on Linux Mint 19.2 Introduction Below steps are described to solve some trouble during and after installation of Quartus Prime Standard ...
Clock Master Other This page documents the configuration of the Clock Master for the other White Rabbit networks (not 'Production'). Introduction The Clock Mast...
The FAIR Timing Master in the "Betriebsgebäude" BG This is a collection of documents related to the FAIR Timing Master in the "Elektronikraum". Equipment Rack5...
Clock Master Production This page documents the configuration of the Clock Master. Please note the corresponding How To. Introduction The Clock Master is the sou...
How To: eb mon Introduction The original intention about this tool has been to get (simpler) access to data of the White Rabbit PTP core. But as the name suggest...
How To: Etherbone with Wireshark Introduction Wireshark might be useful when you need to inspect Etherbone packages sent via Ethernet, see here. Here are a few h...
Main.EnkhboldOchirsuren 14 Aug 2019 How To: Burst generation this functionality is under development and not available in any release A simple solution for gener...
WR ZEN aka SSK Introduction The timing team (TOS) operates a couple of distinct White Rabbit networks. The most important one is a network called production, tha...
Exploder5a Commissioning Guide Note: This test is functional. It is not intended to cover verification validation tests of the design! Note: Software/Version ...
How To: snoopy spy Introduction This is a simple command line tool and provided by one of our colleagues from FEC and available on the ASL 7 cluster. Altho...
Cherry Release V4 (OUTDATED) The Cherry Release is partly compatible with the the Balloon release. * ECA et al should be compatible * But ... * there ...
Balloon Release (OUTDATED) The Balloon Release is NOT COMPATIBLE with the snapshot "January 2016" or previous releases or snapshots. If you want to test or integr...
Release Asterisk v2 (for miniCS) and updates compatible with SaftLib ( OUTDATED ) Asterisk is compatible to the control system releases R3, R4, R5 and R6 The rele...
How To: LM32 Soft CPU Simple Stack Check Introduction This how to demonstrates how a simple check for possible stack violation has been implemented. Principle...
Installing Quartus under Ubuntu 14.04 (and possibly others) THIS HOWTO IS DEPRECATED Introduction This page contains a few notes on installing Altera's Quartu...
Snapshot "January 2016" The intention of this snapshot is twofold. First, to make improvement of White Rabbit available at GSI. Second, to provide again a consist...
How To: eb fwload Introduction This tool has been written to ease software development form lm32 Soft Cores. It allows to upload firmware to one or more Soft Cor...
How To: Installation of a Timing Receiver THIS HOWTO IS DEPRECATED Introduction Installation of a timing receivers should be easy and straight forward. The phy...
Timing Messages: How To test the ECA queue from LM32 Soft CPU and PC Introduction The specified ECA queue is used to storage timing events filtered by eventID. T...
How to Build and Deploy the Timing Run Time Environment THIS HOWTO IS DEPRECATED The documentation here describes a version of the script that has never been pu...
Building and Deployment for a Specific Kernel and Installation into a Staging Directory THIS HOWTO IS DEPRECATED Remark: This is really special. The information...
WR Switch: How To Cross Compile DIM THIS HOWTO IS DEPRECATED This describes the first try to cross compile DIM for a White Rabbit switch. DIM is a communication...
WR Switch: Basic Remote Monitoring (Deprecated) THIS HOWTO IS DEPRECATED This describes how basic remote monitoring of White Rabbit switches can be done by usin...
WR Switch: How To Cross Compile Hello World THIS HOWTO IS DEPRECATED This describes how I cross compiled hello world for switch Getting the Tools This assumes ...
WR Switch: How To Use a WR Switch THIS HOWTO IS DEPRECATED This is just a short list of things I found useful Login to a Switch * ssh via the management po...
WR Switch: How To Flash a WR Switch THIS HOWTO IS DEPRECATED Introduction Most importantly, you should the WRS manual. For version 4.2, see here. Basically, al...
hdlmake auf ein Ubuntu System installieren (Deprecated) THIS HOWTO IS DEPRECATED hdlmake ist ein Präprozessor um VHDL include files und VHDL source files in die...
Installieren Quartus II auf ein Ubuntu System: THIS HOWTO IS DEPRECATED * Download Quartus von https://www.altera.com/download/sw/dnl sw index.jsp * Quart...
Timing System within miniCS THIS HOWTO IS DEPRECATED After reflashing and upgrading the SCUs to 64bit, the timing system of release R1 is no longer operational!...
Hello World on lm32 Soft CPU THIS HOWTO IS DEPRECATED A soft CPU based on the lm32 is embedded in the White Rabbit core. This how to describes a "Hello World" f...
Installation of Tool Chain for the lm32 Soft CPU THIS HOWTO IS DEPRECATED A soft CPU based on the lm32 is embedded in the White Rabbit core. This how to describ...
Tool Chain for a SPEC Board. THIS HOWTO IS DEPRECATED A soft CPU based on the lm32 is embedded in the White Rabbit core. This how to describes the installation ...
FAIR Timing Receiver Node: How To Configure and Operate a VME Timing Receiver (outdated) THIS HOWTO IS DEPRECATED August 2013 Introduction The VETAR2 is the ne...
How To: Installation of a Timing Receiver or SCU THIS HOWTO IS DEPRECATED This how to summarizes the steps required to install a timing receiver. Setup up a FE...
BEL projects building HOW TO THIS HOWTO IS DEPRECATED Prerequistes The following packages are required to build BEL projects: $ sudo apt get install build esse...
How To: eb info Introduction This tool has been written to get information on gateware and firmware actually employed. Usage Usage: eb info OPTION w ...
How To: LM32 Soft CPU Handle the ECA message signaled interrupts (MSIs) Introduction The ECA unit is capable to send MSI on certain conditions, such as: * p...
Main.MichaelReese 22 Aug 2017 Vetar2a: VME WB bridge direct access mode The normal mode of operation (after reset) of the Vetar2a card uses a VME wishbone bridge...
Pseudo SRAM Access from lm32 Introduction The W968D6DA provides 256Mbit (32MByte) of Pseudo SRAM (datasheet). It provides 32 bit address width and 16 data lines....
The Timing System and its Context in the Accelerator Control System What is described here has been compiled from the Common Specifications for the Accelerator Co...
Etherbone Performance Measurements Introduction Access to Wishbone (WB) slaves in the FPGA from the host system is a prominent use case for the accelerator contr...
Deprecated Documents This is just a unrevised collection of outdated or deprecated documents. * Feature List for a Timing Receiver Node at GSI/FAIR (09/2014)...
Documentation Some documentation is given here. This is not structured but just a collection of various things. * Documents * HOW TOs * Releases * Cur...
Timing Receiver: Event Condition Action Unit Figure: A Timing Receiver embedded in a Front End Computer. The core component is the Event Condition Action unit (...
Essentials Figure: Building blocks required for a single 'timing event' Bang!. Components of the General Machine Timing (GMT) are shown in blue. Components requ...
Introduction to the General Machine Timing System The FAIR facility involves a long chain of accelerators which need to be tightly synchronized. An important cons...
SCU Kernel Task Switching Latency Introduction The hardware group (thx to Stefan!) has investigated task switchting / preemption on the SCU kernel with RT patch ...
How To: WB_FEC This wiki provides information about * WB FEC VHDL module and integration in Bel_Projects * Synthesis of Timing Receiver Gateware with the WB...
Data Master: How To Configure and Operate There are different versions of the data master depending on the release of the control system. * Release R12 "Cherr...
Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...
WR Simulation How To This How To guide you in the simulation of the WR Core and WR Switch. Setup the Simulation environment You need a ModelSim runnig in your sy...
Clock Master: How To Operate Introduction This How To is intended for the members of the timing team. The clock master is the White Rabbit Grandmaster Clock of t...
Data Master: How To Configure and Operate for Release R11 ("Cherry") Introduction This How To is intended for the members of the timing team. The data master is ...
Step by step guide to commissioning a new pexaria5: 1 Place powered off pexaria5 on ESD desk , ESD dischare! 1 Attach wrex2a addon board to baseboard WR1 (W...
Data Master: How To Configure and Operate for Release R3 R9 ("Balloon") DEPRECATED Introduction This How To is intended for the members of the timing team. The d...
Data Master: How To Configure and Operate for Release R10 ("Pre Cherry") DEPRECATED Introduction This How To is intended for the members of the timing team. The...
MSI/IRQ Latency Measurements with LM32, Etherbone and Saftlib In autumn 2017, the latency of Message Signalled Interrupts (MSI) has been measured involving differ...
How To: WR LLDP This how to describes how to use LLDP in WR Devices. It is not meant to clarify what is LLDP. Info (November 2017): The development is already in...
GPSDO The GPSDO serves as a primary reference time source for the timing system. Amongst the interfaces, there are three Gigabit Ethernet ports for NTP servers. ...
Main.MichaelReese 30 Sep 2016 Saftlib is constructed around the DBus IPC system. In order to maintain and develop the library, a fairly good understanding of the ...
Snapshot April 2017 DON'T USE THIS SNAPSHOT!!! IT WAS DECIDED TO CANCEL THE ROLL OUT. This snapshot became necessary due to updates of the so called "function...
How To: LM32 Soft CPU Send a Command to a LM32 Soft CPU Introduction This how to demonstrates how to send a command to LM32 Soft CPU. This how to demonstrates ...
How To: LM32 Soft CPU Using MIL Devicebus Introduction This how to demonstrates how to access a device on a MIL Devicebus connected to the SCU ("MIL piggy"). A...
How To: LM32 Soft CPU Accessing a LM32 Soft CPU via shared memory and Wishbone Introduction This how to demonstrates how to access the LM32 Soft CPU via Shared...
How To: LM32 Soft CPU Accessing Another SoC Wishbone Device Introduction This how to demonstrates how to access another Wishbone device on the same SoC from th...
Acronyms These acronyms are focused on the timing system, but may contain other acronyms of the accelerator complex as well. Unclear Acronyms acronyms to be clar...
Vetar2a Commissioning Guide Note: This test is functional. It is not intended to cover verification validation tests of the design! Needed components for each...
Irradiation of Fibres at SIS18 Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be possible, that fibres to ...
Main.MathiasKreider 07 May 2015 Getting Information about the Firmware on a device Firmware IDs The eb info tool was used to read out the build id ROM, providin...
Timing Network Introduction There are several instances of timing networks on the campus. * production: Strictly reserved for specific machines. Presently (sp...
White Rabbit Cabling on the GSI/FAIR Campus Cable Specifications * Fiber Optic ITU T G.652 c or d * Wavelength transmission/reception 1490nm/1310nm *...
VETAR2 (Release R1) The VETAR2 is a VME carrier board that can be White Rabbit enabled using the VETAR1DB2 add on board. I/Os are defined by a mezzanine board. H...
FESA Properties for DataMaster Class (current version running on vmla03) Global Interface (Device Name MCS_DM_GLOBAL) Setting Properties * Command * dataM...
The XML Format Used by the Data Master The DM uses an XML format to describe a schedule. Presently (09/2014), this format depends on implementation details. A (no...
Feature List for Timing Receivers at GSI and FAIR This page lists some hardware features for timing receivers at GSI and FAIR. Some recommended features will beco...
EXPLODER2C (Release R1) The EXPLODER2C is a carrier board for a stand alone device based on an ArriaII FGPA. It can be White Rabbit enabled using the WREX1 add on...
SCU2 (Release R1) The SCU (Scalable Control Unit) is the standard front end controller used by the CSCO group based on an ArriaII FPGA. It can be White Rabbit ena...
PEXARIA5 (Release R1) The PEXIARA5A is a PCIe carrier board based on an ArriaV FPGA. It can be White Rabbit enabled using a WREX1 add on board. I/O are implemente...
Black_Cat1 Mezzanine Board The Black Cat mezzanine board extends the PEXARIA5 board with I/Os. However, the WR1 connector on Black Cat is no longer used, as the W...
FMC Module SIXIO2 The FMC module SIXIO2 has been designed by Jan Hoffmann / EE. It's purpose is simple I/O. * Info by EE: Some figures and specs * Sixio2_SC...
BuTiS Receiver Station The BuTiS receiver station are maintained by the RF group, contact persons are P. Moritz or B. Zipfel. Setup Figure 1: BuTiS receiver sta...
Data Master: How To Configure and Operate for Release R1 This describes the temporary solution derived from miniCS (July 2013). This information is outdated, as...
PEXARIA5DB The PEXIARA5DB is a mezzanine card for a PEXARIA5 carrier board. It exists in two variants. * PEXARIA5DB1, with IDC connector for LVDS signals: sche...
Network Equipment under the Responsibility of CSCOTG Cables, equipment and White Rabbit Switches are maintained using a database. Simple Viewer A simple viewer c...
Irradiation of Fibres at HHD Cave (SIS18 beam dump) Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be poss...
Connection to EE Labor This is just a temporary document, to be replaced by some proper documentation. Note on calculating cable lengths The cable length has bee...
Feature List for Add On boards of Timing Receivers at GSI and FAIR This page lists some hardware features for add on boards. Such add on boards are mezzanine boar...
FAIR Timing/GSI Timing Team Core members of the GSI Timing Team are: T.Fleck C.Prados S.Rauch M.Kreider Further leading actors within the GSI controls group are U...