50 recent changes in Timing Web retrieved at 13:55 (GMT)

TimingSystemHowDebugSaftlibWithGDB
Remote debugging of a running saft daemon with GDB It is possible to connect GDB to a running SCU, set breakpoints, step through the code, print variables, etc. T...
r2 - 13 Oct 2021 - 12:19 by MichaelReese
WebNotify
* .AndreasReiter: * * .DietrichBeck: * * .EnkhboldOchirsuren : * * .HaraldBraeuning: * * .MichaelReese: * .RalphBaer: * * .NikolausKurz: * * ...
MonitorLocalSystemTimeOfWRSviaSNMP
Monitor local system time of a WRS via SNMP 1. Introduction WRS synchronises its local time with an external NTP server, if one is specified in CONFIG_NTP_SERVER...
TimingSystemHowConfigureWRMILGW
WR MIL gateway Introduction WR MIL gateways are a replacement for the existing SIS and ESR Pulszentrale (PZ). They are implemented in software running on a LM32 s...
r27 - 08 Jun 2021 - 10:00 by MichaelReese
TimingSystemHowPhtif
How To: Poor Humans TIF An Ugly Temporary TIF Workaround for the 2021 Beam Time Introduction As there is currently no replacement for the MIL TIFs with the new...
TimingSystemPEXPTestingAndCommissioning
PEXP Testing and Commissioning Guide Attention: This guide does not check the whole PCIe standard! Attention: This is NOT for FAT Required component...
TimingSystemDocumentRep20210218
Saftlib Latency Measurements During the startup of the accelerator in February 2021, issues have been observed with the so called function generator (FG): Occasio...
TimingSystemDiagnostics
Reading the DM status To get an overview on whats running on a DM, you can get the basic status by issuing root@tsl017 ~ # dm cmd dev/wbm0 or root@tsl017 ~ # dm...
NEW - 17 Feb 2021 - 15:29 by MathiasKreider
TimingSystemErrorMsg
Documentation of Data Master Error Messages Parser Errors caused by faulty schedule data If any of the following error messages are reported to you or appear in ...
NEW - 17 Feb 2021 - 13:55 by MathiasKreider
TimingSystemHowToVersand
Sending Stuff from GSI Elsewhere THIS HOWTO IS DEPRECATED Requirements * ebiss Account @ GSI, see here * Account number ("Kostenstelle" or "Auftragsnumme...
TimingSystemTMIS
How To: TMIS Introduction TMIS (Timing Message Information Service) is a quick evaluation on distribution of timing messages via the ACC controls network. The ma...
Members
GSI Timing Team Core members of the GSI Timing Team are: F. Ameil (associated): work package lead (FAIR) D. Beck: operation, tools and docs, legacy stuff for UNIL...
TimingSystemHowEventSnoopTool
Timing Messages: How To Snoop the Timing System News FEC for FESA class is now scuxl0143. Introduction This is a first simple solution to view what is going on ...
FlashingWithEthernetBlaster
How To: Configuring and using Altera Ethernet Blaster to flash DM PRO * Download current gateware archive, unpack * Copy jic file to tmp directory on tsl021...
r2 - 22 Jan 2021 - 09:50 by MathiasKreider
TimingSystemHowPCSetup
How To: Setting Up a Linux Box Intended usage: E Release For older releases please check out the history of this Wiki page. Introduction This how to describes se...
TimingSystemHowSaftCtl
How To: saft ctl Introduction This tool is intended to diagnose the status saftlib and provide ECA related information of a timing receiver. Moreover one can do ...
r5 - 10 Dec 2020 - 11:03 by MichaelReese
TimingSystemHowSaftDm
How To: saft dm Introduction This tool (saft dm: "saft Data Master") is intended to provide a primitive Data Master for local operations in the FEC. This tool mi...
r3 - 10 Dec 2020 - 11:00 by MichaelReese
TimingSystemButisInterface
White Rabbit, BuTiS, Clocks and Time Introduction Two systems exist for distribution of time stamps and clocks: 1. The General Machine Timing System provides ...
TimingSystemNodesCurrentRelease
This pages just includes the page of the current release. For editing that page, go here.
TimingSystemPexaria5TestingAndCommissioning
Testing and Commissioning Guide for Pexaria5 Required components * Pexaria5 under test (named as P5UT in this guide) * PC with Intel Quartus (version 18...
TimingSystemERelease
Enigma Release (DEPRECATED) Previous releases are Asterisk, Balloon, Cherry and Doomsday. This release has been replaced by release Fallout. New Features and Bu...
TimingSystemDocumentsGateFirmWare
Gateware and Firmware Gateware and firmware are provided with releases. * Gateware: synthesized (V)HDL code * Firmware: compiled code for the lm32 soft CPU ...
TimingSystemRelease
Releases and Snapshots of the Timing System Release A Timing Firmware Release packs together new features and requirements defined in our Development Road Map, ...
TimingSystemHowSaftIoCtl
How To: saft io ctl Introduction Use this tool to configure I/Os and setup rules for I/Os in the ECA. Usage IO CTL for SAFTlib Usage: saft io ctl OPTIONS Ar...
TimingSystemHowTRRegistration
How To: Connecting a Timing Receiver to the White Rabbit Network A timing receiver MUST NOT be connected to a White Rabbit network without authorization. Authori...
TimingSystemHowSoftCPUCompiler
How To: LM32 Soft CPU Compiler Introduction This how to describes the status and how to build the compiler for the lm32 soft cpu. Links * on github (for be...
TimingSystemHowDevAcc
How To: Poor Man's (d, m, w) Path to Device Access Introduction This How To is not even a how to. Instead, it is just a collection of stuff required to develop a...
TimingSystemEvent
Timing Messages Format of a Timing Message Timing messages is a term describing the input to a Timing Receiver (TR) that possibly leads to generation of a so cal...
TimingSystemWRSWitchNewHW
White Rabbit Switch Hardware 4.0 Overview This page summarizes the GSI requirements in context with the development of a new version of the White Rabbit Switch. ...
TimingSystemHowSaftLcd
How To: saft lcd Introduction This is a an experimental GSI specific command line tool for live display of Beam Production Chains (BPC). Usage via Command Line ...
TimingSystemGSTrUsage
Timing Receiver: Usage For using a Timing Receiver (TR) please follow the directions here. What is Needed * TR hardware, see here what is supported by the cur...
TimingSystemNetworkBasics
(Some) Basics of Networking and White Rabbit The prime source for information for White Rabbit project is the Open Hardware Repository. The aim of this page is to...
WebStatistics
Statistics for Timing Web Month: Topic views: Topic saves: File uploads: Most popular topic views: Top contributors for topic save and uploads: ...
TimingSystemHowSoftCPU
How To: LM32 Soft CPU Introduction Soft CPUs are a VDHL implementation of a CPU in a FPGA. With FAIR Timing Receivers, Soft CPUs are directly embedded in the Wis...
TimingSystemDocumentRep20191010
Report: Latency and Loss of Timing Messages in the Timing System Introduction Starting in October 2019 the ECA Tap module was added to the gateware of a few dedi...
TimingSystemAMCTestingAndCommissioning
AMC Testing and Commissioning Guide Required components for each uTCA device * SFP (green/purple) * LC cable and a white rabbit switch (Recommended: RUN...
TimingSystemHowQuickStart
How To: Quick Start THIS HOWTO IS DEPRECATED (look in the /bel_projects readme) The following will provide you with "master" of our our repository. 1 git clo...
r6 - 03 Dec 2019 - 14:53 by MarcusZweig
TimingSystemPolicies
Policies in the Timing Network * The timing network is managed by TOS and TOS defines the policies. * The timing network is a "field bus" synchronizing the...
TimingSystemDoomsdayRelease
Doomsday Release (DEPRECATED) Previous releases are Asterisk, Balloon and Cherry. This release is replaced by Enigma. New features and bug fixes in Doomsday Rel...
Saftlib2MigrationGuide
Main.MichaelReese 07 Feb 2019 In response to user requests for lower latency communication and fewer library dependencies in saftlib, API breaking changes are int...
r30 - 12 Nov 2019 - 08:42 by MichaelReese
Quartus16InstallMint191
Installing Quartus 18.1 on Linux Mint 19.2 Introduction Below steps are described to solve some trouble during and after installation of Quartus Prime Standard ...
TimingSystemClockMasterOther
Clock Master Other This page documents the configuration of the Clock Master for the other White Rabbit networks (not 'Production'). Introduction The Clock Mast...
TimingSystemDocumentsMaster
The FAIR Timing Master in the "Betriebsgebäude" BG This is a collection of documents related to the FAIR Timing Master in the "Elektronikraum". Equipment Rack5...
TimingSystemClockMaster
Clock Master Production This page documents the configuration of the Clock Master. Please note the corresponding How To. Introduction The Clock Master is the sou...
TimingSystemHowEbMon
How To: eb mon Introduction The original intention about this tool has been to get (simpler) access to data of the White Rabbit PTP core. But as the name suggest...
TimingSystemEBWireshark
How To: Etherbone with Wireshark Introduction Wireshark might be useful when you need to inspect Etherbone packages sent via Ethernet, see here. Here are a few h...
TimingSystemHowGenerateBursts
Main.EnkhboldOchirsuren 14 Aug 2019 How To: Burst generation this functionality is under development and not available in any release A simple solution for gener...
TimingSystemDocumentRep20190911
WR ZEN aka SSK Introduction The timing team (TOS) operates a couple of distinct White Rabbit networks. The most important one is a network called production, tha...
TimingSystemNodesReleaseAsteriskExploder5aCommission
Exploder5a Commissioning Guide Note: This test is functional. It is not intended to cover verification validation tests of the design! Note: Software/Version ...
TimingSystemHowSnoopy
How To: snoopy spy Introduction This is a simple command line tool and provided by one of our colleagues from FEC and available on the ASL 7 cluster. Altho...
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Topic revision: r1 - 09 Jan 2009, ProjectContributor
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