Description of the features for the UNILAC Datamaster

This describes the planned features for the UNILAC datamaster. The features were presented at the Workshop UNILAC Controls Roadmap 2024 to 2026.

WR 2 MIL Connection 7xSCU

Hardware / HEL

7 SCUs which transform WR events into MIL events. These replace the UNILAC MIL Gateway.

Planned effort: 1 Month

UNI-DM Server Hardware

Hardware / TOS

Order and setup datamaster servers as described in the table of instances.

Planned effort: 1 Month

Details

new UNILAC integration system test-network needed. Communication DM_FAIR DM_ICU via Localmaster_Production Localmaster_UNILAC.

UNI-DM Server Hardware (test system): host and 1 pexarria5 with gateware for UNI-DM. This has 2 CPUs, an ECA, and WB-master. The host needs saftlib (version ?) to feed messages from DM_FAIR to DM_ICU. The host needs FESA.

To be clarified: transfer of messages from DM_ICU to DM_FAIR needed? The 4 CPUs of DM_FAIR are independent, thus it is possible to separate the 4 CPUs on two DMs if more memory is needed on DM.

50Hz Phase Detection Hardware

Hardware / HEL

Build an interface card which detects 50Hz phase signals an communicates these to a timing receiver.

Planned effort: 1 Month

50Hz Phase Processing

Software / TOS

Implement the processing of the 50Hz signals: jitter, smooth synchronization

Planned effort: 4 Month

Timing Msg 2 WB-Bus

Software / TOS

Implement sending timing messages to a Wishbone bus.

Planned effort: 4 Month

DM Referencing

Software, DM firmware, schedules

Implement new node type, which allows referencing to values at specified memory locations. May be used to timestamp a beam chain.

Planned effort: 1 Month

DM Static Register Nodes

Software, DM firmware, schedules

Implement new node type, which describes general purpose registers for the schedules.

Planned effort: 2 Month

DM Branching ALU Nodes

Software, DM firmware, schedules, DM tools

Implement new node type 'calculating nodes'. These are nodes which describe operations for an ALU (arithmetic logic unit) and which describe branching on conditions.

Planned effort: 3 Month

MASP 2 DMs Communication

Software, DM firmware

Implement the communication between MASP and the UNILAC datamaster.

Planned effort: 3 Month

Ring-DM 2 UNI-DM Communication

Software, DM firmware

Implement the communication between two datamasters, one for ESR, Cryring, SIS, the other for UNILAC.

Planned effort: 3 Month

UNI-DM Graph Template

???

Planned effort: 3 Month

50Hz Phase Loop

Software, DM firmware

Implement the handling of the incoming 50Hz events.

Planned effort: 2 Month

Integration

Software, testing.

Integration of ???.

Planned effort: 6 Month

Datamaster Instances

Instance	Maschine	Hardware	Remarks
PROD SIS CRYRING ESR	tsl017.acc.gsi.de	ProLiant DL380 Gen9
PROD SIS CRYRING ESR Backup	tsl018.acc.gsi.de	ProLiant DL380 Gen9
PROD UNILAC
PROD UNILAC Backup
PROD Ion Sources			to be clarified
PROD Ion Sources Backup			to be clarified
INT SIS CRYRING ESR	tsl020.acc.gsi.de	ProLiant DL380 Gen9
TTF	tsl014.acc.gsi.de		Backup for itself with another timing receiver (pexarria)
User	fel0101.acc.gsi.de	Supermicro
Developement			Timing Labor

• v0.3uni-presi-23-07-19.pdf: Datamaster Presentation for the Workshop UNILAC Controls Roadmap 2024 to 2026