Interface to BuTiS

Here, the interface between the FAIR timing system and BuTiS is described.

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For high-precision synchronization beyond the parameters of the GMT (e.g. distributed rf- and kicker-control, bunch-to-bucket transfers, time-of-flight measurements) a Bunch Timing System (BuTiS) will distribute high precision clock trains (100 kHz ident pulse, 10 MHz sine). A propagation delay compensation is achieved by the use of a local reference synthesizer whose internal reference oscillator is phase locked to the distributed 10 MHz sine. A phase-locked 200 MHz clock is generated inside as well as the delayed ident pulse. The phase of the 200 MHz sine-wave clock is precisely adjustable in 1 degree steps (approx 14 picoseconds). Adjustments can be done locally or via ethernet data connection. The phase shift data is derived from the propagation delay measurement system residing at the BuTiS center. An accuracy of about 100 picosends per kilometer and a jitter in the low femtosecond range is achieved.

An overview on the link between the timing system and BuTiS is given below.

timeSystem butisLink.JPG

A combination of a GPS Disciplined Oscillator (GPSDO) receiver and dedicated reference synthesizers is used to create a 10 MHz S1 sine. The S1 signal has a perfect long-term stability combined with a relative short-term (seconds) stability of about 10e-12. In addition, a 100 kHz ident pulse P0 is produced. Both signals S1 and P0 are sent to optical receivers (DWDM) over long distances. The bi-directional optical link allows measuring the link delays precisely. At the BuTiS center, correction data are calculated for each optical link and distributed via an Ethernet network (grey arrows) to so called local reference synthesizers (Ref. Synth.). Short copper links are used to transmit local clocks LP0 and LS1 from the optical receiver the reference synthesizer. At the reference synthesizer, a delay corrected C2 200 MHz sine and T0 100 kHz ident clocks are generated. Both clocks do not only have the same quality as the clocks provided at the BuTiS center but their phase is moreover locked and adjustable relative to the master clock at the BuTiS center. For more information on the reference synthesizer, please have a look here.

More information on BuTiS is given here.

FAIR Timing System and BuTiS

The clock master within the timing master is basically a White Rabbit switch. By using a Clock Divider (see CLOSY) a 10 MHz signal CREF is generated, which is both phase aligned to the 200 MHz c2 clock as well as the 100 kHz T0 clock. The 10 MHz CREF signal is used as an external reference clock for the clock master switch. By this, the carrier frequency of the WR network on the whole FAIR campus is locked to BuTiS.

Via the switched WR network, data is transmitted between the WR master to the WR receivers. Most importantly, such data are the timing events, the PTP protocol providing TAI time stamps, and the phase between the T0 ident clock and "ticks" of the UTC time stamps.

Two examples of WR receivers are shown in the figure above.

This WR receiver is not linked to BuTiS. Processing at a WR receiver is done by using a Field-Programmable Gate Array (FPGA). The clock of the FPGA is linked to the frequency and phase of the 125 MHz Ethernet carrier of the WR network. Besides processing of data, the FPGA resynthesizes the 100 kHz T0 clock of BuTiS at the same frequency and phase, a local reference synthesizer of BuTiS would have. By this, actions can be triggered synchronously to the campus wide BuTiS T0 clock. Such an action could be the generation of simple waveforms, which are available via connectors and can be supplied to equipment via copper links.

The WR receiver is directly linked to a piece of equipment via the backplane. Transfer of timing data to the equipment is done with a fixed phase relative to the 100 KHz T0 signal, that is resynthesized in the FPGA of the WR receiver. For highest timing accuracy, waveform signals are generated at the equipment and synchronized to the 200MHz C2 clock of BuTiS.

Interface to FESA

An important remark: The figure shown above does not show how waveforms to be generated are transmitted to the timing receiver or equipment. Typically, the combination of WR receiver and equipment is treated as a FESA device.

-- DietrichBeck - 24 Sep 2014
Topic revision: r15 - 20 Dec 2017, DietrichBeck
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