SILECS is a framework which is used to:
  • define different plc-configurations in xml-files
  • generate PLC-specific files to run a configuration on a PLC
  • test the configurations via the Silecs-Diagnostic-Tool
  • generate API to connect to the PLC via C++
  • generate FESA components to simplify integration into the GSI control-system

SILECS consists of the following components:
  • silecs-eclipse-plugin - Main Development Tool for Silecs developers ( currently it consists as well of the silecs-code-generation which is written in python )
  • silecs-diagnostic-cpp - Tool in order to test a plc-configurations created with Silecs
  • silecs-communication-cpp - Communication library which is used by "silecs-diagnostic-cpp", the FESA-binary or any other C++ code to connect to PLC's.
  • silecs-makefile - Makefiles which are used to simplify linking for silecs-developers
  • silecs-model - XML-Schemas for the XML Files of silecs

SILECS was originally developed at CERN, however the GSI-specific Silecs differs alot from the CERN version:
  • No central python-server needed
  • Removed any CERN specifics
  • Support of some GSI-specifics ( FESA GSITemplate )
  • Heavily simplified, in order to easy support
  • Only the package "silecs-communication-cpp" is almost the same for CERN and GSI

A 'Silecs Design project' defines the data to be exchanged with a 'controller' (blocks and the registers in a hardware)

A 'Silecs Deploy project' binds several design instances on one/many physical PLC

SILECS stands for "Software Infrastructure for Low-level Equipment Controllers".
Topic revision: r2 - 10 May 2023, MatthiasWiebel
This site is powered by FoswikiCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding Foswiki? Send feedback