-- TobiasHoffmann - 22 Feb 2008

The CERN VME Timing Module CTRV

The CTRV is a CERN VME timing receiver board. So far we have no distributed timing, therefore the module has to be used in a stand-alone mode using its internal counters.

To start and operate the module some scripts and binaries made by CERN have to be used. They are placed on asl715 in:

/acc/dsc/mcr/ppc4/drivers/ctr

Initialization

Log into the front-end Rio3 as root and cd to the /acc/dsc/mcr/ppc4/drivers/ctr directory. Call the script gsictr.sh
This has to be done every time the crate is restarted. OR: put an rc.local file into the path /data/dsc/mrc/[fec-name]/etc which calls the script on reboot.

Usage

To program and control the board one has to use the program ctrvtest. Download the user manual from the attachments from the main wikipage and try out. Especially on the last page there is a list of all commands.

Goal is to create a signal on the outputs and/or as interrupt on the bus. These signals may be used as a trigger for RT actions or as a clock. E.g. one can create a signal on the output to trigger an oscilloscope channel, which is connected to a signal created by an RT action. The same pulse is also created on the bus (backplane of the VME crate) to start the RT action. With this setup the latency time from the trigger until the result can be measured.

A self defined signal which can be selected (in the Instantiation) by Fesa is called a ptm (periphal Timing). With 2.9 this is not possible yet. We have to program the module directly, the settings are kept in the module, even if you have killed the ctrvtest program.

How it works

Each of the 8 channels implements a counter. The counter is loaded on start with a value. It then counts down with each cycle of the master clock. When the counter reaches 0 the programmed action (restart, LEMO output, bus interrupt) is performed. Under remote control (see exmaple below) the counter value loaded on start is specified with the command 'v'.

Thus in the example below, with 'v20' the value 20 is loaded when the counter starts. With a 1kHz master clock, it takes 20/1kHz = 20ms to reach 0. In the first example the counter than restarts itself ('s4'), issues a signal on the LEMO output ('o1') and a bus interrupt ('b1').

Example

Enter all commands within the ctrvtest program, to leave a submenu just enter a dot "." plus enter. By default the module operates with the 1kHz master clock which can be switched to 10MHz and 40MHz with the cnf submode (see below).

Example: We need a 50Hz trigger-rate on channel 1 Lemo output and on the bus to trigger an RT action:

• mo n selects the nth CTR module in the crate, the default is the first one.
• rem 1 (remote 1 because we have no ext. timing cable connected, we work directly on the "remote" module)
• ch1 (selects channel 1)
• cnf (config submode, ready to set parameters, press here ? for options list)
  • w39 (set to 1µs pulse width: always add 1 multiplied with timebase 25ns-> (39+1= 40) * 25ns= 1µs)
  • v20 (the divider of the masterclock. Default 1kHz 1000/20 = 50 Hz)
  • o1 (Mult, the pulse comes multiple times instead of once, burst etc.)
  • s4 (restarts itself)
  • e1 (enable Lemo output)
  • b1 (enable bus interrupt)
  • . (leaves cnf mode)
• wi ? (wait for interrupt, list all channels)
• wi 0x0002 (shows one interrupt with time stamp of channel 1)
• 10 (wi 0x002) (shows next 10 interrupts)
• wi 0 (disconnect from interrupts, reconnect with e.g. wi 0x002)
• qf 1 or qf 0 (interrupt queue off or on)
• ptmwf (write settings to file)
• ptmrf (read settings from file)

It is also possible to enter the settings of the cnf-submode in one row, e.g. s4w39v10k0o1e1b1 to produce a 100Hz clock.

How to use external trigger (e.g. TIF events):

Use all commands mentioned above, but set s to 1 (Ext 1) or 2 (Ext2)

• rem1
• qf 0
• cnf
  • ch1
  • s1
  • ENTER -> ch2
  • s2, o1, v20, w39, v20, e1, b1 .
• wi ?
• wi 2
• wi 4

Testen:

10(wi) (this prints out the next 10 Interrupts)

Note

In this example the bus interrupt is issued 20ms after the external trigger signal. This is because the counter is loaded with the value 20 ('v20') when the external trigger arrives ('s1') but the bus interrupt ('b1') is issued only when the counter reaches 0. With a 1kHz master clock, this means a delay of 20ms.

The output levels are TTL by default, they can be switched rto negative TTl level if required.

Good to know

"Something worth to note is that the phase of your train of pulses is random, but constant, with respect to the PPS(pulse per second); it depends on when you start the counter by inputting the above settings. If you need the phase to be fixed, you'll need a second counter..." (for Details see Email from Ioan Kozsar, 06.03.08)