Ramped Devices (Function Generator)

Description (TODO)

will be a very important class for FAIR controls...

The function generator which is developed for usage in the FAIR facility implements polynomal interpolation (quadratic order).

The function generator requires a constant stream of interpolation data. While one interpolation is executed, the data for the next interpolation must be provide. Especially when one front-end controller handles several function generators, the real-time capability of FESA would not be sufficient to ensure providing interpolation data in time. Therefor control of the function generator is implemented in a program on softcore processor (LM32) which provides fast reaction times, because the processor doesn't run an operating system. The FESA-class only interacts with the function generator program on the softcore processor, communication via a common memory.

Internally, the function generator implements integer arithmetic. Calculating with integer arithmetic, quadratic interpolation can lead to untolerable rounding errors. Care has to be taken in adjusting the distance between interpolation points: Starting with a set of interpolation points, the resulting errors in the ramp generation must be calculated. If the resulting Errors are too high, then interpolation points must be defined more closely.

The FESA-class for the function generator should provide for acquisition data. For sampling the acquisition data, in principle two possibilities can be seen: Either take acquisition data at the interpolation points, which wold provide for easy comparison with the seting data, or take acquision data at regular distances.

some remarks:

It is expected that each function generator may have different length of interpolation sections. Because of quadratic interpolation, the shape of the ramps may request that interpolation sections start at different point in times for different devices. So it cannot be expected that all devices request for new interpolation parameters at the same time. May lead to timing problems: When a real-time action has to be started to provide new interpolation parameters, start delay may accumulate then.

Is it clear how to acquire acquisition data? When ADC wil be triggered, who triggers ADC? Today trigger is at end of interpolation section - this will not be sufficient, especially when length of interpolation sections is not equidistant.

Keep in mind: Even optimized FESA (Linux real-time patches, adjusted process priorities, ...) has jitter in interrupt reaction time (jitter in start of real-time actions) of more than 100 µs, with a total delay of more than 150 µs.

CRYRING-Equipment

The FESA class 'ramped devices' has to support the equipment which is installed in the CRYRING. This holds for

• ramped power supplies ring- and electron-cooler-magnets, ramped RF ramped, several flavors, always SCU with AD/DA and/or digital I/O cards
  • digital set and acquisition values, for one output channel
  • analogue set and acquisition values, generally up to 12 data sets to independently drive 12 magnets (1 compound power supply with up to 12 independent output channels)
  • cooler HV supply, analoue set value (18 bit), two analogue acquisition values (voltage, current)
  • cooler HV supply, five on one SCU, each analogue set value, two analogue acquisition values (voltage/current?)
  • RF, serviced by PBRF (ring RF), needs amplitude (analogue) and frequency (digitial, for DDS)
• interfacing types to be supported
  • SCU/ACU (FAIR standard)
  • MSL-interfaces, on SCU (CRYRING-equipment from Manne Siegbahn Laboratory, Sweden)
    • interfacing is implemented by a set of general digital I/O and ADC/DAC cards
  • MIL-bus interfaces (via GSI interface card), to connect to some re-used existing GSI power supplies

Property Layout

Setting properties

IMPORTANT: Every setting property has standard items to the ones listed here.

property name	prop. type	field	type	unit	comment	impl
Init	init				Resets InterlockBits (if not set anymore)
Reset	reset					not yet
Setting	setting	coeffArrCurr	2D double array	A	polynominal coefficients (t, a, b, c)
		coeffArrVolt	2D double array	V	polynominal coefficients (t, a, b, c)

Acquisition properties

IMPORTANT: Every acquisition property has standard items to the ones listed here.

property name	prop. type	field	type	unit	comment	impl
Status	status	detailedStatus	int	See extra table	See extra table
		standard status items			standard items for status property
Acquisition	acquisition	detailedStatus	bool array	-	See extra table
		detailedStatus_labels	2D char array		names for the status bits
		coeffArrCurrSet	2D double array	A	polynomial coefficiences (t, a, b, c)
		coeffArrVoltSet	2D double array	V	polynomial coefficiences (t, a, b, c)
		curent	double array	ampère	Actual values of the device
Version	version

All acquistion properies implement an internal "onChange" behaviour.

detailedStatus_bit_number	meaning	detailedStatus_label
0	?	dummy0
1	?	dummy1
2	?	dummy2
3	?	dummy3

Description of the Hardware (TODO)

• What does it do?
• Set values
  • Current (in A)
  • for some device types Voltage (in V)
• Actual values
  • Current and/or Voltage (depends on device type)
• Status
  • Error
  • Status
  • Inerlock Bits
• ...

Interface to the Equipment (SCU/ACU communication)

Following device interfaces have to be supported:

SCU/ACU (FAIR standard)

• The SCU communicates with the ACU via SCU-Bus. First information -> SCU Testing
• Equipment is represented by registers in ACU
  • The forseen registers are described in the ACU register layout.
  • Access from SCU is via Etherbone
  • ...
• ...

MSL interface

• a set of digital I/O and ADC/DAC hardware is used

MIL-bus interface (via GSI interface card)

• ...

Operation of the Device (TODO)

Multiplexing and Timing Control

• Usage of timing?

Initial Values, Persistency

• where to start from?
• which data to be persistent?

Functionality of the Front-End Software

• On/Off (-> any procedure needed?)
• Reset
• Precision (time/values)

FESA version

2.0.1