WR Simulation How-To

This How-To guide you in the simulation of the WR Core and WR Switch.

Setup the Simulation environment

You need a ModelSim runnig in your system. This How-To uses ModelSim 10.0c on Arch Linux.

The installation and setup of ModelSim is unfortunately platform dependent. Here, a link of the fantastic wiki of Archlinux with some troubleshootings installing ModelSim, it may help you.

If you have another version of ModelSim and Linux distribution, I wish you a lot of luck with your installation.

Altera Simulation Libraries

Before you start simulating you need to generate the simulation libraries. Altera offers a command line command to generate it.

sudo $(QUARTUS)/quartus_sh --simlib_comp -tool modelsim -family arriav -language vhdl

Change the family if you're using another FPGA (e.g. arriaii) Unfortunately ModelSim 10.0c needs to install these libraries with sudo, it is a bad idea but I didn't find another way...

You need a running Altera Quartus framework.

Xilinx Simulation Libraries

Before you start simulating you need to generate the simulation libraries. Xilinx offers a gui to set up your libraries. (You need a running Xilinx ISE framework with a valid license)

sudo $(XILINX)/bin/compxlib

This gui will navigate you through and compile the libraries.

HDLMAKE

You need to install in your system the HDLMAKE from the OHWR. The testbenches are built only (at least for me) for the HDLMAKE v2.1 About the installation of HDLMAKE check the wiki and the available documentation. The installation depends on your system and the Python version that you're using.

Simulating WR Core and related cores

1. Clone the wr-cores repository from the OHWR

2. cd wr-cores/testbench/wrc_core
   

3. hdlmake
   

4. make
   

5. sudo vsim
   

After this command ModelSim will start and the simulation will be carried out

*To the date 12/11/2017 the only release with working simulation was the wrpc-v4.0 release.

Simulating WR Switch

You need a running Xilinx ISE framework.

1. Clone the repository from the OHWR
2. Follow the how-to in this link

3. cd wr-switch-hdl-test/testbench/scb_top_8p 
   

4. hdlmake
   

5. make
   

6. sudo vsim
   

After this command ModelSim will start and the simulation will be carried out.

*To the date 12/11/2017 the only testbench working properly was the scb_top_8

-- CesarPrados - 08 Nov 2017