Snapshot April 2017


This snapshot became necessary due to updates of the so-called "function generator". Although these update concern mainly VHDL, a new version of saftlib+drivers is required too. A snapshot was required to prepare for a roll-out of the control system for the CRYRING tests and beam time starting spring/summer 2017.

New features and bug-fixes of this Snapshot

  • White Rabbit core version 4
  • Added DBus file descriptors to saftlib
  • saft-ctl -> fixed BPID indicator

Known Issues of this Snapshot

  • todo
  • ...

Supported Hardware

The hardware supported in this Snapshot:

Form Factor Carrier WR add-on Commissioning Remark
PCIe PEXARIA5A WREX1 PEXARIA5DB1/2 click "fixed" PEXARIA5 boards are compatible
SCU3 SCU3 on carrier (MIL)  
Table: Hardware for nodes.

Timing Receiver Nodes

Gateware Images

Type FPGA Bitstream CPLD Bitstream date
PEXARIA5A pci_control_csco_tr.rpd, sof pexaria5-cpld.jed 2017-Apr-24
EXPLODER5A exploder5.rpd, sof exploder5-cpld.jed 2017-Apr-24
SCU2 scu_control2.rpd, sof -- 2017-Apr-24
SCU3 scu_control3.rpd, sof -- 2017-Apr-24
VETAR2A vetar2a.rpd, sof -- 2017-Apr-24
Table: Bitstream tarballs for the Timinmg Receiver Nodes.

Info about the FPGA and CPLD Bitstreams, here


Type Path in SL7 Servers Comment
build environment for software N/A provided by CSCOFE
run-time system for timing /common/export/timing-rte/tg-snapshot_240417 nfsinit: 20_timing-rte -> ../global/timing-rte-tg-snapshot_240417
Table: Software.

Data Master


Getting the sources code of the Snapshot from our GIT Repository

If you want to check the source code this Release is in the branch "proposed_master_test_03302017" in bel_projects, the snapshot is marked by the tag "snapshot_240417".

How to...

Know if my FEC is booting from Snapshot Run Time Environment

Possibility 1: View Info Files


[ruth@scuxl0815 ~]# cat /etc/os-release 
GSI embedded release 7 (build 2017-04-06)

If that file does not exist or includes different information, please contact CSCOIN.

Timing Run Time Environment

[ruth@scuxl0815 ~]# cat /etc/timing-rte_buildinfo 
GSI embedded release 7 (build 2017-04-06)
[root@scuxl0038 ~]# cat /etc/timing-rte_buildinfo 
GSI Timing RTE 26-04-2017_10-41-49 
Compiled by ahahn using ./ on - Linux  3.10.0-514.10.2.el7.x86_64
CI_CD Project
 - master*@78f1d67
 - snapshot_240417@85c5b1a
 - Nothing to commit

Most important information to check:
Bel Projects CI_CD
snapshot_240417@85c5b1a master*@78f1d67

Possibility 2: Using Tools


[ruth@scuxl0815 ~]# uname -r

In case of a different kernel, please contact CSCOIN.

Etherbone and Saftlib Version

[ruth@scuxl0815 ~]# eb-mon -e dev/wbm0
etherbone 2.1.0 (balloon-3-gcb8c807): Feb 10 2017 13:09:27 / built by ahahn on Apr 26 2017 10:40:35 with running CentOS Linux release 7.3.1611 (Core)

[ruth@scuxl0815 ~]# saft-ctl bla -fi
saftlib source version                  : saftlib 1.0.9 (v1.0.9-16-g5bf9d91): Apr 24 2017 11:45:47
saftlib build info                      : built by ahahn on Apr 26 2017 10:41:42 with running CentOS Linux release 7.3.1611 (Core) 

Most important information to check:
Etherbone Version Saftlib Version
balloon-3-gcb8c807 v1.0.9-16-g5bf9d91

Know if I Have a Valid Firmware

[ruth@scuxl0815 ~]# eb-info dev/wbm0
Project     : scu_control
Platform    : scu3 +comexpress
FPGA model  : Arria II GX (EP2AGX125EF29C5)
Source info : zenith-1387
Build type  : snapshot_240417
Build date  : Mon Apr 24 15:30:30 CEST 2017
Prepared by : Stefan Rauch <>
Prepared on : belpc098
OS version  : Ubuntu 16.04.2 LTS, kernel 4.4.0-72-generic
Quartus     : Version 16.0.2 Build 222 07/20/2016 SJ Standard Edition

  85c5b1a saftlib: saft-pps-gen improvement
  826ea8d saftlib: reintroduced fd
  123cdaa saftlib: changed branch (gentle saft-pps-gen version)
  7f6bb0d monster: moved white rabbit core to top cross bar
  6b64dc4 monster: fix out butis clock for Arria2

Most important information to check:

Build type Source Info Last Commit Build Data
snapshot_240417 zenith-138 85c5b1a >= 24 Apr 2017

Test a Timing Receiver running Snapshot

If you need timing events for integration purposes or testing, connect your FEC in the Integration System and you will get events from the Snapshot-Data Master.

Another option is to inject events from the Run Time System, this related how-to can help you.


Types of Bitstream Platform Description How to Flash or Program
rpd Altera Raw Programming Data File. This file contains the TR Gateware. It's used to write the gateware into the flash memory of the TR. It is persistent eb-flash
sof Altera SRAM Object File. This file contains the TR Gateware. It's used to write to program the FPGA. It is not persistent Quartus Programmer
jic Altera JTAG Indirect Configuration File. This file contains the TR Gateware. It's used to program the FPGA. It is not persistent Quartus Programmer
jed Xilinx This file contains the special Gateware for the CPLD on the TR. It is persistent Xilinx Programmer

More Information

  • building and deployment of software and drivers (including SCU), see here and here
  • flashing timing receivers with new images (including SCU), see here
  • some hints for FECs, see here

-- DietrichBeck - 26 Apr 2017
I Attachment Action Size Date Who Comment
exploder_snapshot240417.tar.gzgz exploder_snapshot240417.tar.gz manage 4 MB 26 Apr 2017 - 11:34 DietrichBeck bitstream for exploder
pci_control_snapshot240417.tar.gzgz pci_control_snapshot240417.tar.gz manage 4 MB 26 Apr 2017 - 11:34 DietrichBeck bitstram for pexaria
scu2_snapshot240417.tar.gzgz scu2_snapshot240417.tar.gz manage 4 MB 26 Apr 2017 - 11:35 DietrichBeck bitstream for SCU2
scu3_snapshot240417.tar.gzgz scu3_snapshot240417.tar.gz manage 4 MB 26 Apr 2017 - 11:36 DietrichBeck bitstream for SCU3
vetar2a_snapshot240417.tar.gzgz vetar2a_snapshot240417.tar.gz manage 3 MB 26 Apr 2017 - 11:36 DietrichBeck bitstram for vetar
Topic revision: r5 - 05 May 2017, DietrichBeck
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