How-To: eb-rest


This tool has been written to easy 'reset of FPGA'. This cycles the FPGA and (re)loads the image from the flash to the FPGA. Use tool is useful for
  • gateware updates via the flash (see How-To: Flash)
  • recovery of a SCU in case the OS has hung up
On a SCU, a 'reset' will also force a reboot of the COM Express board, thus all software like FESA will be hardly terminated (and hopefully restarted after reboot).


Usage: eb-reset [OPTION] <etherbone-device> [command]

  -e               display etherbone version
  -p<t>            after FPGA reset, wait for the specified time [s] and probe device
  -h               display this help and exit

  wddisable        disables the watchdog (preventing automated FPGA reset permanently)
  wdenable         enables the watchdog (automated FPGA reset after 'some time')
  wdretrigger      retriggers an enabled watchdog (preventing automated FPGA reset for 'some time')
  wdstatus         gets the status of the watchdog; '1': enabled, '0': disabled
  phyreset         resets the PHY (recommended for experts and developers)
  sfpreset         resets the SFP (recommended for users)
  cpuhalt <cpu>    halts a user lm32 CPU
                   specify a single CPU (0..31) or all CPUs (0xff)
  cpureset <cpu>   resets a user lm32 CPU, firmware restarts.
                   specify a single CPU (0..31) or all CPUs (0xff)
  cpustatus        get the 'halt status' of all user lm32 (rightmost bit: CPU 0)
  fpgareset        resets the entire FPGA (see below)

Use this tool to reset a FPGA or lm32 user CPU(s).

The command 'fpgareset' forces a restart of the entire FPGA using the image stored in the 
flash of the device. Don't use this command unless the flash contains a valid image (otherwise
your devices becomes bricked).

Report software bugs to <>
Version 1.3.0. Licensed under the LGPL v3.

  • Using this tool via the White Rabbit network might be unreliable, as unicast UDP packets might get lost. In case of an error message, just try again.
  • Use the '-p' option allows verifying the FPGA is operational again after 'reset'.

-- DietrichBeck - 4 Nov 2022
Topic revision: r3 - 04 Nov 2022, DietrichBeck
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