Enigma Release

Previous releases are Asterisk, Balloon, Cherry and Doomsday.

This release will be replaced by release F.

New Features and Bug-fixes in Enigma Release

  • 2019-Jul-02: [v5.0.0] pre-alpha release
    • (hopefully) fixed an issue with PCIe direct access under 64 bit
    • saftlib 2.0 (see wiki, presentation)
    • watchdog for SCU gateware: the watchdog resets the FPGA every ~10 minutes, unless it is disabled from the operating system
    • new lm32 toolchain; used by TOS and HEL; includes some bug fixes and run-time check of stack health
    • refurbished bel_projects build system
    • includes 'Quartus seed finder'
    • includes support for 'ACO jenkins'
    • migration to Quartus 18.1
    • saftlib with UTC support
  • 2019-Aug-19: [v5.0.1] alpha version and first release
    • saftlib 2.1 (see wiki, presentation)
    • WR-MIL gateway is now integrated in saftlib
    • DM-UNILAC gateway refactoring
    • DM supports mixed command sequences from BSS and LSA
  • 2019-Sep-11: [v5.0.2]
    • seed for VHDL synthesis for PMC and AMC changed
    • PCIe bridge includes timeout handling for Wishbone cycles not properly closed by the host system
  • 2019-Oct-21: [v5.0.3]
    • SCU: FG firmware with 'rescan fix'
    • saftlib v2.1.1
      • 'rescan fix'
      • improved UNILAC snooping
    • eb-mon
      • previous option '-s' (WR sync) now available as option '-y'
      • added option 'snoop mode' that allows continous monitoring
      • added diagnostic for continuity of White Rabbit time
      • added diagnostic for eCPU stalls (data bus)
      • added diagnostic for ECA-TAP (requires a dedicated gateware image)
    • makefile: added $target-sort to sort qsf files
    • hotfix 2019-nov-12: disabled 'socat'
  • 2019-Dec-17: [v5.0.4]
    • EB: promiscuous bug fix
    • saftlib v2.1.2
    • eb-mon
      • time offset (option '-o'): now with fractional milliseconds
      • representation of latency changed for 'snoop mode'

Readme

Developers should read this.

Known Issues of Enigma Release

  • 2019-Aug-19: flashing devices may be touchy
    • using eb-flash-secure instead of eb-flash will reduce the risk of ending up with a bricked device
  • 2019-Aug-19: caveat for builing RTE
    • requires manual action when building RTE
  • 2019-Aug-19: fix broken FESA
    • FESA depends on some libraries not present in the INN ramdisk. These are added to the RTE by the timing team as we are nice people.
  • 2019-Aug-19: clock generator has strange phase offset
    • to be reviewed, irrelevant for most frontends
  • 2019-Aug-19: power cycle of WRS might brake node tracking
    • requires major rework -> next release
  • 2019-Aug-19: 'lock LED' might be unreliable
    • requires major rework -> next release
  • 2019-Aug-19: no WR lock after power cycle of node
    • requires major rework -> next release
  • 2019-Aug-19: serdes clock gen
    • requires major rework -> next release
  • 2019-Sep-02: 64bit issue with old TLU
    • only relevant for DAQ/MBS, not urgent, continue with 32bit OS for now
    • issue closed on 2019-Sep-09
  • 2019-Sep-11: flashing PMC via MENA20X PCI fails sometimes
    • please use this command to flash the PMC timing receiver eb-flash -s 0x10000 -w 3 dev/wbm{X} pci_pmc.rpd
  • 2019-Oct-25: 'make' of eb tools ignores PREFIX
    • only relevant for installations without sudo privileges
  • 2019-Oct-30: BOOTP goes crazy
    • this may happen under special circumstances; PLEASE REGISTER YOUR EQUIPMENT
  • 2019-Oct-31: hardware bug
    • some PEXARIA5C and EXPODER5B devices have a hardware issue caused by improper usage of the 'output enable' pin of a 2nd flash chip
    • those boards must be repaired before they may be used; risk of a bricked device
  • 2019-Nov-13: Promiscuous Mode
    • Timing Receivers are configured in promiscuous mode.
    • fixed by enigma 5.0.4
  • 2019-Nov-20: Issue with occasional (1-2 per week) late events
    • bug hunt ongoing

Wishlist for Upcoming Minor Releases

  • fix 'promisuous bug'
  • fix issue with late events

Release Compatibility Matrix

Release Name Date Release Version Gateware PXE config Timing RTE Etherbone Saftlib Ramdisk Type GIT hash
Enigma pre-alpha 2019-Jul-02 5.0.0 5.0.0 N/A timing-rte-tg-enigma-v5.0.0-pre-alpha 2.1.0 2.0.0 2019-05-08 pre-alpha 9f5c79b
Enigma (alpha) 2019-Aug-19 5.0.1 5.0.1 (SCU), link N/A timing-rte-tg-enigma-v5.0.1-alpha 2.1.0 2.1.0 2019-08-12 alpha AND release efb4199
5.0.0 (Other), link              
Enigma 2019-Sep-11 5.0.2 5.0.2, link N/A timing-rte-tg-enigma-v5.0.2 2.1.0 2.1.0 2019-08-12 release dcd625a
Enigma 2019-Oct-21 5.0.3 5.0.3 (SCU), link N/A timing-rte-tg-enigma-v5.0.3 2.1.0 2.1.1 2019-08-12 release f95a3127
5.0.2 (Other), link
Enigma 2019-Dec-17 5.0.4 5.0.4, link scuxl.enigma timing-rte-tg-enigma-v5.0.4 2.1.0 2.1.2 2019-08-12 release fe2ff8f
Table: Version matrix. Color coded are entries require flashing (gateware) or changing symbolic links (PXE config, Timing RTE). Listed are current (green) and old (red) releases.

Just in Case: Nightly builds for the Enigma gateware/firmware/software are available here.

Setting up Timing Receiver Nodes

Follow these steps 1. Gateware Image
  • please download gateware images 'rpd' by following the link in the table above
  • downloaded images must be written to a flash chip on each individual timiming receiver hardware; see here for flash instructions.

2. Ramdisk (ACO environment only)
  • make sure the host system is (via PXE) booting the ramdisk specified in the table above
  • information on the PXE boot process is described here
  • typically, you just need to create a symlink < HOSTNAME > -> < PXE-CONFIG >

3. Timing Runtime (RTE, ACO environment)
  • use the RTE configuration specified in the table above
  • information on nfs-init is described here
  • typically, you just need to create a symlink 20_timing-rte -> ../global/timing-rte-tg-enigma-v< VERSION >
  • other OS: follow the directions given in this how-to

4. Socat
  • socat has been disabeld
  • if you need socat
    • create a symlink 90_timing-socat -> ../global/timing-rte-tg-socat
    • reboot
    • the use of socat is forbidden in the production environment

Checking Timing Receiver Nodes

Follow these steps

1. Gateware Image Version
[ruth@scuxl0815 ~]# eb-mon -a dev/wbm0
Enigma-v5.0.4

2. Ramdisk Version
[ruth@scuxl0815 ~]# cat /etc/os-release
GSI embedded release 7 (build 2019-08-12)

3. Timing Runtime Version
[ruth@scuxl0815 ~]# cat /etc/timing-rte_version
5.0.4

4. Timing Runtime Buildinfo
[ruth@scuxl0815 ~]# cat /etc/timing-rte_buildinfo
GSI embedded release 7 (build 2019-08-12)
[root@scuxl0175 ~]# cat /etc/timing-rte_buildinfo 
GSI Timing RTE 11-12-2019_13-31-30 
Compiled by ahahn using ./build-rte.sh on asl743.acc.gsi.de - Linux  3.10.0-957.27.2.el7.x86_64
CI_CD Project
 - https://github.com/GSI-CS-CO/ci_cd.git
 -  master*@cbbf44d
BEL_PROJECTS
 - https://github.com/GSI-CS-CO/bel_projects.git
 - enigma-v5.0.4@fe2ff8f
Last Commits in repo:
fe2ff8f saftlib: v2.1.2
ceb9915 microtca: changed fitter seed
c33fd07 vetar2a-ee-butis: changed fitter seed
e6c987a README.md: updated
9b8f71e Merge pull request #202 from GSI-CS-CO/enigma-v5.0.3-bugfix-promiscous

Trouble? Follow the steps given here

Supported Hardware

Form Factor Carrier WR add-on Commissioning Remark
standalone EXPLODER5A WREX1/WREX2A EXPLODER5ADB2 click
PCIe PEXARIA5XX WREX1 PEXARIA5DBYY click "fixed" PEXARIA5 boards are compatible
SCU2 SCU2 WREX1 (MIL)  
SCU3 SCU3 on-board (MIL)  
VME VETAR2A WREX1 VETAR1DB2A click  
AMC tr-amc on-board N/A  
PMC tr-pmc on-board N/A  
Table: Supported hardware.

Further Reading

Bitstream Types

Types of Bitstream Platform Description How to Flash or Program
rpd Altera Raw Programming Data File. This file contains the TR Gateware. It's used to write the gateware into the flash memory of the TR. It is persistent eb-flash
sof Altera SRAM Object File. This file contains the TR Gateware. It's used to write to program the FPGA. It is not persistent Quartus Programmer
jic Altera JTAG Indirect Configuration File. This file contains the TR Gateware. It's used to program the FPGA. It is not persistent Quartus Programmer
jed Xilinx This file contains the special Gateware for the CPLD on the TR. It is persistent Xilinx Programmer

Data Master

Sources for Data Master images and software are part of the GIT repository in dedicated branches.

Getting the sources code of the Enigma Release from our GIT Repository

If you want to check the source code this Release is in the branch 'enigma' in bel_projects.

git clone git@github.com:GSI-CS-CO/bel_projects.git  // try 'git clone https://github.com/GSI-CS-CO/bel_projects' if not using public/private key authentification
cd bel_projects
git checkout enigma
make

More Information

  • building and deployment the Timing Run-Time Environment, see here
  • building and deployment of software and drivers for various types of linux boxes (including SCU), see here and here
  • flashing timing receivers with new images (including SCU), see here
  • some hints for FECs, see here

-- DietrichBeck - 18 December 2019
Topic revision: r34 - 15 Jan 2020, AlexanderHahn
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