The FAIR Timing Master in the "Betriebsgebäude" BG

This is a collection of documents related to the FAIR Timing Master in the "Elektronikraum".


Rack54 Rack55 Rack56
Clock Master I (PRO) ACCNET Switch  
Clock Master II (SSK) Management Master  
BuTiS Receiver Station Data Master  

Rack Planning

The figure below indicates the planning of the racks hosting the Timing Master and the related infrastructure.


Figure: Rack Planning.
The figure just serves to estimate the number of racks required.

-- DietrichBeck - 29 Oct 2019
Topic revision: r10 - 29 Oct 2019, DietrichBeck
This site is powered by FoswikiCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding Foswiki? Send feedback