Feature List for Timing Receivers at GSI and FAIR

This page lists some hardware features for timing receivers at GSI and FAIR. Some recommended features will become required in the future. Electronic part numbers are only examples.

  1. SFP cage
  2. WR circuitry
  3. host bus interface (if applicable)
  4. power LEDs for all voltages
  5. FPGA: 5AGXMA3D4F27I3N for all platforms except SCU, which uses EP2AGX125.
  6. status information via LED on front panel
  7. flash for gateware and firmware; consider serial (N25Q256A13GF840E) flash for Arria 5 GX.
  8. one-wire EEPROM for hardware model, hardware revision number, calibration data and MAC address (DS28EC20P)
  9. one-wire ROM temperature sensor with serial number (DS18B20U+)
  10. USB port using a USB peripheral controller, CY7C68013A-56BAXC. This is required as
    • serial interface for the WR console and
    • Etherbone via USB
  11. UART or USB port. In case serial console is implemented via a secondary USB port, a USB to UART bridge (such as CP2101) shall be used
  12. JTAG connector
  13. logic analyzer port
  14. digital I/O is implemented depending on the form factor
    • on the carrier board or
    • on a mezzanine board
  15. reset button

Numbers are approximate only and derived from the Asterisk release. Furthermore, FPGA RAM needs to be located closely to the logic using it. As other restrictions must be considered too, the numbers given here don't tell the full story.
  • Available
    • EP2AGX125...: approx 6.6 MBit (already used: about 80% including FEC but without "user lm32")
    • 5AGXMA3D...: approx 10.5 MBit
  • Required
    • FECo: RAM required for FECo (erasure channel decoding): 320kbit for buffering 24 full Ethernet frames + 1MBit for lm32 RAM.
    • ECA unit and Action Queues: About 530kBit for the ECA. Receiving components must be considered separately. As an example, the action queue (PCIe transfer) requires 82kBit.
    • lm32 cluster: Depends on the configuration. The default value is about 1MBit per CPU but this value had to be reduced to 0.5 MBit already in the current (09/2014) gateware for the case of the SCU.
    • Additional on-board SRAM would be nice to have.

  1. display on front panel
  2. EEPROM > 20kByte for for configuration data, could also be a partition of the gateware flash
  3. power connector for usage as standalone receiver
  4. action button, type of action defined by gateware

your stuff

-- DietrichBeck - 25 Sep 2014
Topic revision: r13 - 25 Sep 2014, DietrichBeck
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