-- DusanSlavinec - 22 Sep 2016

Pmc5a Commissioning Guide

Note: This test is functional. It is not intended to cover verification & validation tests of the design!

Note: Software/Version of bel_projects used in this tutorial: hash@ branch

Needed components for each Pmc5a device

  • SFP (green/purple)
  • LC cable and a white rabbit switch
  • USB cable (micro)
  • Power supply (if you don't use the PMC carrier)
  • Xilinx programmer (Platform Cable USB II, DLC10)
  • Altera usb blaster
  • OLE display module (UG-2864ASYDT03)
  • LEMO cable(s) + 2 pin cable(s) (need for LVDSo/i 10 pin boxed header)

Important Steps

Programming the CPLD

  1. Check out bel_projects
  2. Turn on power
  3. Attach Xilinx programmer to the JTAG adapter PROMOx and connect mircro USB cable to on board jtag (xilinx programmer)
  4. Run ISE
  5. Load project bel_projects/syn/gsi_pmc/cpld/pmc_prog.xise
  6. Process Menu => Implement Top Module
  7. Tools Menu => Impact
  8. Double-click Boundary Scan
  9. Control-I => pmc_prog.jed
  10. Operations Menu => Program
  11. Turn power off

Check White Rabbit clock

  1. Confirm that WR clock PLL output frequency is 125MHz by measuring it on the bottom side of the board near FPGA (capacitors C369, C370)
  2. If frequency is not 125MHz then check configuration resistors for WR PLL (see schematic)
  3. Turn power off

Programming the FPGA

  1. Turn power on
  2. (altera usb blaster)
  3. If this does not work: Use the JTAG2USB adapter
  4. Open Quartus Programmer and program the FPGA (or use the command line: quartus_pgm -c 1 -m jtag -o 'p; pci_pmc.sof')
  5. Write this bit-stream into the SPI flash: eb-flash dev/ttyUSBx pci_pmc.rpd (in case USB is already programmed)

Programming the USB Chip

  1. Run 'make' in bel_projects/ip_cores/etherbone-core/hdl/eb_usb_core
  2. Make sure, that no other timing receiver is attached with USB
  3. Erase the USB controller (as root): ./flash-fx2lp.sh -E
  4. Program the USB controller (as root): ./flash-fx2lp.sh
  5. Turn power off and on
  6. Program the FPGA again: quartus_pgm -c 1 -m jtag -o 'p; pci_pmc.sof'
  7. Configure the SPI flash chip: eb-config-nv dev/ttyUSBx 10 4
  8. Format the 1-wire EEPROM in bel_projects/ip_cores/wrpc-sw/tools
  9. ./eb-w1-write dev/ttyUSBx 0 320 < sdb-wrpc.bin
  10. Write this bit-stream into the SPI flash: eb-flash -i 1 dev/ttyUSBx pci_pmc.rpd (in case FPGA is not programmed)

Check White Rabbit

  1. eb-console dev/ttyUSBx
  2. Type in "gui", white rabbit status should be: locked and calibrated
    Synchronization status should be:
    + Servo state: TRACK_PHASE
    + Phase tracking: ON
    You should also see 4 leds at the front panel:
    + red = traffic/no-link
    + blue = link
    + green = timing valid
    + white = PPS
  3. Press ESC to quit
  4. Type in "mode master", node should be able to lock the PLL and become a master
    Quit console
  5. Turn power off and on

Check EEPROM and set MAC

  1. Run eb-console dev/ttyUSBx
  2. Set MAC address for the device #xy: <<mac setp 00:26:7b:00:02:XX>>, Control-C
  3. Turn power off and on
  4. Run eb-console dev/ttyUSBn
  5. Type in "mac", you should see the previously entered MAC address
  6. If you don't have a DHCP server, you can set an ip address by "ip set 192.168.100.xyz"

Check IOs

  1. Go to the tools directory
  2. Make io-test
  3. Connect IOx and IOy (check that every IO works as input and output)
  4. ./io-test dev/ttyUSBx

Check PCI

  1. Try the following tools (with dev/wbm{n}):
    • eb-info dev/wbmn
    • eb-ls dev/wbmn
    • eb-console dev/wbmn
  2. Write to internal shared ram and read it back:

    • Get the LM32 shared ram address by eb-ls dev/wbmn
    • Example output: 3.2 0000000000000651:81111444 84000 LM32-RAM-Shared
    • Create a dummy file (which will be written into the ram): dd if=/dev/urandom of=foo bs=4k count=1;
    • Write dummy file to the lm32 shared ram: eb-put dev/wbmn 0x84000 foo
    • Get the data from the shared ram: eb-get dev/wbmn 0x84000/4096 bar
    • Compare both files: cmp foo bar
    • Both files should contain the same data
    • Repeat this test in a loop... (optional)

Check PCI interrupts

  1. The device must be attached to the carrier with PMC slot
  2. Try cat /proc/interrupts ( | grep wb ), there should be one irq number with pcie_wb handler
  3. Use saft-ctl name snoop 0 0 0 to snoop for the incomming events
  4. You should see list of incoming events in your console now

Optional Steps

Check LEDs

  1. saft-pps-gen name -s (this tool will output a PPS on every channel and all LEDs connected to FPGA)
  2. You can change the OE setup by saft-io-ctl

Check Buttons

  1. Go to bel_projects/tools
  2. make
  3. ./button-game dev/ttyUSBn
  4. Press every button, make sure that you saw one event for every button at least. Be aware, that the buttons are not debounced

Check Display

  1. Connect via JTAG USB
  2. Attach the display
  3. Go to bel_projects/modules/ssd1325/demo/exploder5_demo
  4. make all
  5. Upload the demo to lm32: make test
  6. Display should show the device status now

Check RAM

  1. Create a test file with dd: dd if=/dev/urandom of=put_file bs=33554432 count=1 (32MB; 32*1024*1024)
  2. Get the address of the pseudo ram controller by eb-ls dev/ttyUSBx (26 0000000000000651:169edcb7 4000000 Pseudo SRAM)
  3. Put the file into the ram by eb-put dev/ttyUSBx 0x4000000 put_file
  4. Read back the file from ram by eb-get dev/ttyUSBx 0x4000000/33554432 get_file
  5. Compare the files: cmp put_file get_file

Check OneWire Devices

  1. Go to: tools/commissioning/onewire-scanner
  2. make
  3. run application: ./onewire-scanner dev/ttyUSB0
  4. There should be 2 controllers and 4 devices (and no unknown devices)


  • White Rabbit/Ethernet
  • JTAG (board)
  • JTAG (usb)
  • USB connection
  • LEDs (4xWR, 4xUSER, 1xBASE Power (green), 1xADDON Power (white), 6xLVDSi/o), 8xIO OE, 8xIO ACT)
  • Buttons
  • IOs
  • Display
  • RAM
  • OneWire devices
  • PCI + Interrupts


Type rpd sof jic jed (cpld) date
Exploder5a Test-Image exploder5_csco_tr.rpd.xz exploder5_csco_tr.sof.xz exploder5_csco_tr.jic.xz exploder5_cpld.jed Oct 2015
Topic revision: r2 - 22 Sep 2016, dslavin
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