library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;  

use work.vhpi_example.all;

entity testbench is
end entity;

architecture simulation of testbench is


begin

  process
    variable integer_ret : integer;
    variable bit_ret : bit;
    variable std_logic_ret: std_logic;
    variable std_logic_vector_ret: std_logic_vector(1 to 16);
    variable std_logic_vector_test: std_logic_vector(31 downto 0) := x"11111111";
    variable simple_rec : simple_record := (10, 'Z');
  begin
    -- string
    constrained_string_proc("hallo welt"); -- string of 10 characters
    string_proc("hallo welt!!!!!"); -- string of 10 characters

    -- integer
    integer_ret := integer_fun(42);
    report "integer_ret = " & integer'image(integer_ret);
    report "-------------";

    -- bit
    for bit_arg in bit loop
      bit_ret := bit_fun(bit_arg);
      report "b_arg = " & bit'image(bit_arg);
      report "bit_ret = " & bit'image(bit_ret);
      report "-------------";
    end loop;

    -- std_logic
    for std_logic_arg in std_logic loop
      std_logic_ret := std_logic_fun(std_logic_arg);
      report "std_logic_arg = " & std_logic'image(std_logic_arg);
      report "std_logic_ret = " & std_logic'image(std_logic_ret);
      report "-------------";
    end loop;

    -- std_logic_vector
    report "std_logic_vector_test = " & integer'image(to_integer(signed(std_logic_vector_test)));
    std_logic_vector_proc(std_logic_vector_test);
    report "std_logic_vector_test = " & integer'image(to_integer(signed(std_logic_vector_test)));
    std_logic_vector_proc_out(std_logic_vector_test);
    report "std_logic_vector_test = " & integer'image(to_integer(signed(std_logic_vector_test)));

    -- record
    simple_record_proc(simple_rec);

    wait;
  end process;



end architecture;