/*
 * scu_echo_test.h
 *
 *  Created on: 27.01.2012
 *      Author: localadmin
 */

#ifndef SCU_ECHO_TEST_H_
#define SCU_ECHO_TEST_H_

#define MASTER_STATUS			0x0		/* r/w */
#define MASTER_G_INT_ENA		0x1		/* r/w */
#define MASTER_VERS				0x2		/* r */
#define MASTER_SRQ_ENA			0x3		/* r/w */
#define MASTER_SRQ_ACTIVE		0x4		/* r/w */
#define MASTER_SRQ_IN			0x5		/* r */
#define MASTER_WR_MULTI_S_SEL	0x6		/* r/w */
#define MASTER_ECHO_1			0x7		/* r/w */
#define MASTER_ECHO_2			0x8		/* r/w */

#define S_ID					0x01	/* r */
#define S_FW_VERSION			0x02	/* r */
#define S_FW_RELEASE			0x03	/* r */
#define S_HW_VERSION			0x04	/* r */
#define S_HW_RELEASE			0x05	/* r */
#define S_VERS_REVI_MACRO		0x06	/* r */
#define S_ECHO					0x10	/* r/w */
#define S_STATUS				0x11	/* r */

#define S_INTR_IN				0x20	/* r */
#define S_INTR_ENA				0x21	/* r/w */
#define S_INTR_PENDING			0x22	/* r/w */
#define S_INTR_MASK				0x23	/* r/w */
#define S_INTR_ACTIVE			0x24	/* r/w */

#define 	bit_scub_wr_err			(1 << 0)
#define 	bit_scub_rd_err			(1 << 1)
#define		bit_ti_cyc_err			(1 << 2)
#define		bit_inval_intern_acc	(1 << 3)
#define		bit_inval_slave_nr		(1 << 4)
#define		bit_scub_srqs_active	(1 << 5)


volatile int master_srq_active;		/* holds active irqs from the slaves */
volatile int error_occured = 0;			/* error flag for irq handler */
unsigned char const *scu_base = (unsigned char*)SCU_MASTER_0_BASE;


/* macros for accessing scu bus master */
#define SCUB_RD(SLAVE_NO, REG_ADR)  		*((int*)build_addr(SLAVE_NO, REG_ADR))
#define SCUB_WR(SLAVE_NO, REG_ADR, WRDATA)  *((int*)build_addr(SLAVE_NO, REG_ADR)) = WRDATA

#endif /* SCU_ECHO_TEST_H_ */