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DBBasedAnalysisOfTimingMessages
Main.MathiasKreider 01 Dec 2021 Using snoop outputs for analysis of what's going on in the accelerator Purpose * One Thing * Lorem ipsum ... ...
NEW - 02 Dec 2021 - 09:33 by MathiasKreider
ExcessivePtpAndLldpTraffic
WR PTP synchronization of WRS under excessive PTP and LLDP traffic 1. Introduction The White Rabbit (WR) technique is specially developed to provide sub nanose...
NEW - 27 May 2022 - 13:34 by EnkhboldOchirsuren
SaftlibEtherboneLm32LatencyMeasurement
MSI/IRQ Latency Measurements with LM32, Etherbone and Saftlib In autumn 2017, the latency of Message Signalled Interrupts (MSI) has been measured involving differ...
r5 - 30 Nov 2017 - 14:24 by MichaelReese
SnoopAnalysisBoosterTest1
Booster Test November 2021 Introduction The so called 'Booster Mode' shall be used to accumulate beam from multiple SIS18 injections into SIS100 at a rate of abo...
r10 - 22 Dec 2021 - 09:26 by DietrichBeck
TimingSystemBallonRelease
Balloon Release (OUTDATED) The Balloon Release is NOT COMPATIBLE with the snapshot "January 2016" or previous releases or snapshots. If you want to test or integr...
r26 - 20 Aug 2019 - 07:27 by DietrichBeck
TimingSystemCherryRelease
Cherry Release V4 (OUTDATED) The Cherry Release is partly compatible with the the Balloon release. * ECA et al should be compatible * But ... * there ...
r9 - 20 Aug 2019 - 07:28 by DietrichBeck
TimingSystemDocumentRep20180131
Etherbone Performance Measurements Introduction Access to Wishbone (WB) slaves in the FPGA from the host system is a prominent use case for the accelerator contr...
r9 - 15 Jan 2019 - 12:46 by DietrichBeck
TimingSystemDocumentRep20180904
SCU Kernel Task Switching Latency Introduction The hardware group (thx to Stefan!) has investigated task switchting / preemption on the SCU kernel with RT patch ...
r6 - 27 Sep 2018 - 14:40 by DietrichBeck
TimingSystemDocumentRep20190221
Pseudo SRAM Access from lm32 Introduction The W968D6DA provides 256Mbit (32MByte) of Pseudo SRAM (datasheet). It provides 32 bit address width and 16 data lines....
r3 - 21 Feb 2019 - 10:46 by DietrichBeck
TimingSystemDocumentRep20190911
WR ZEN aka SSK Introduction The timing team (TOS) operates a couple of distinct White Rabbit networks. The most important one is a network called production, tha...
r8 - 20 Sep 2019 - 12:42 by DietrichBeck
TimingSystemDocumentRep20191010
Report: Latency and Loss of Timing Messages in the Timing System Introduction Starting in October 2019 the ECA Tap module was added to the gateware of a few dedi...
r8 - 27 Dec 2019 - 11:46 by DietrichBeck
TimingSystemDocumentRep20210218
Saftlib Latency Measurements During the startup of the accelerator in February 2021, issues have been observed with the so called function generator (FG): Occasio...
NEW - 18 Feb 2021 - 09:25 by DietrichBeck
TimingSystemDocuments
Documents Table of Contents Technical Documents General Machine Timing System * Timing System @ GSI * Master (10/2019) * Network (04/2015) ...
r148 - 22 Apr 2024 - 05:45 by DietrichBeck
TimingSystemDocumentsRep201607222
Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...
r6 - 30 Jan 2018 - 09:55 by DietrichBeck
TimingSystemDocumentsRep20211222
Booster Test December 2021 TL;DR For 'booster mode': * timing the beam transfer from UNILAC to SIS18 works with ~98% efficiency, if rf conditioning at UNILAC ...
r6 - 13 Jan 2022 - 09:04 by DietrichBeck
TimingSystemIrradtionHHD
Irradiation of Fibres at HHD Cave (SIS18 beam dump) Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be poss...
r3 - 22 Apr 2024 - 05:44 by DietrichBeck
TimingSystemIrradtionSIS18
Irradiation of Fibres at SIS18 Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be possible, that fibres to ...
r9 - 22 Apr 2024 - 05:43 by DietrichBeck
Number of topics: 17
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