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TestIeee1588NetworkAdapters
Test the interoperability of the IEEE 1588 capable network adapters with the White Rabbit switches Introduction This report presents the interoperability between...
TimingSystemAMCTestingAndCommissioning
AMC Testing and Commissioning Guide Required components for each uTCA device * SFP (green/purple) * LC cable and a white rabbit switch (Recommended: RUN...
TimingSystemAcronyms
Acronyms These acronyms are focused on the timing system, but may contain other acronyms of the accelerator complex as well. Unclear Acronyms acronyms to be clar...
r9 - 19 Sep 2016 - 15:45 by MichaelReese
TimingSystemBallonRelease
Balloon Release (OUTDATED) The Balloon Release is NOT COMPATIBLE with the snapshot "January 2016" or previous releases or snapshots. If you want to test or integr...
TimingSystemBuTiSReceiver
BuTiS Receiver Station The BuTiS receiver station are maintained by the RF group, contact persons are P. Moritz or B. Zipfel. Setup Figure 1: BuTiS receiver sta...
TimingSystemButisInterface
White Rabbit, BuTiS, Clocks and Time Introduction Two systems exist for distribution of time stamps and clocks: 1. The General Machine Timing System provides ...
TimingSystemCherryRelease
Cherry Release V4 (OUTDATED) The Cherry Release is partly compatible with the the Balloon release. * ECA et al should be compatible * But ... * there ...
TimingSystemClockMaster
Clock Master Production This page documents the configuration of the Clock Master. Please note the corresponding How To. Introduction The Clock Master is the sou...
TimingSystemClockMasterOther
Clock Master Other This page documents the configuration of the Clock Master for the other White Rabbit networks (not 'Production'). Introduction The Clock Mast...
TimingSystemContext
The Timing System and its Context in the Accelerator Control System What is described here has been compiled from the Common Specifications for the Accelerator Co...
TimingSystemDBusInfo
Main.MichaelReese 30 Sep 2016 Saftlib is constructed around the DBus IPC system. In order to maintain and develop the library, a fairly good understanding of the ...
r16 - 15 Sep 2017 - 09:10 by MichaelReese
TimingSystemDMUniPZ
Gateway Data Master UNILAC PZ (dm unipz) Introduction "dm unipz" is the interface between the White Rabbit based Data Master und the MIL based UNILAC 'Pulszentr...
TimingSystemDataMaster
Data Master Manuals DM Technote: DM Manual. A DM Firmware and API Documentation. WIP, about 80% complete. Still trying to keep up with all the implemented feature...
TimingSystemDataMasterTestSystem
Documentation Data Master Test System Hardware SuperMicro fel0069 The data master for the test system is hosted on SuperMicro fel0069 with two PEXARIA5d (fel006...
TimingSystemDataMasterTestsHowTo
How to run and develop tests for the Datamaster Run Tests with pytest The folder modules/ftm/tests has a Makefile. The important targets are: all, remote, prepar...
TimingSystemDataMasterUnilac
Description of the features for the UNILAC Datamaster This describes the planned features for the UNILAC datamaster. The features were presented at the Workshop U...
TimingSystemDataMasterXMLFormat
The XML Format Used by the Data Master The DM uses an XML format to describe a schedule. Presently (09/2014), this format depends on implementation details. A (no...
TimingSystemDeprecatedDocumentation
Deprecated Documents This is just a unrevised collection of outdated or deprecated documents. * Feature List for a Timing Receiver Node at GSI/FAIR (09/2014)...
TimingSystemDeprecatedHowTo
Deprecated HOW TOs This is just a unrevised collection of outdated or deprecated HOW TOs. Timing Receivers * Building and Installation * HOW TO: Instal...
TimingSystemDiagnostics
Reading the DM status To get an overview on whats running on a DM, you can get the basic status by issuing root@tsl017 ~ # dm cmd dev/wbm0 or root@tsl017 ~ # dm...
NEW - 17 Feb 2021 - 15:29 by MathiasKreider
TimingSystemDocumentRep20180131
Etherbone Performance Measurements Introduction Access to Wishbone (WB) slaves in the FPGA from the host system is a prominent use case for the accelerator contr...
TimingSystemDocumentRep20180904
SCU Kernel Task Switching Latency Introduction The hardware group (thx to Stefan!) has investigated task switchting / preemption on the SCU kernel with RT patch ...
TimingSystemDocumentRep20190221
Pseudo SRAM Access from lm32 Introduction The W968D6DA provides 256Mbit (32MByte) of Pseudo SRAM (datasheet). It provides 32 bit address width and 16 data lines....
TimingSystemDocumentRep20190911
WR ZEN aka SSK Introduction The timing team (TOS) operates a couple of distinct White Rabbit networks. The most important one is a network called production, tha...
TimingSystemDocumentRep20191010
Report: Latency and Loss of Timing Messages in the Timing System Introduction Starting in October 2019 the ECA Tap module was added to the gateware of a few dedi...
TimingSystemDocumentRep20210218
Saftlib Latency Measurements During the startup of the accelerator in February 2021, issues have been observed with the so called function generator (FG): Occasio...
TimingSystemDocumentation
Documentation Some documentation is given here. This is not structured but just a collection of various things. * Documents * HOW TOs * Releases * Cur...
TimingSystemDocuments
Documents Table of Contents Technical Documents General Machine Timing System * Timing System @ GSI * Master (10/2019) * Network (04/2015) ...
TimingSystemDocumentsAddOnBoardFeatures
Feature List for Add On boards of Timing Receivers at GSI and FAIR This page lists some hardware features for add on boards. Such add on boards are mezzanine boar...
TimingSystemDocumentsBlackCat1
Black_Cat1 Mezzanine Board The Black Cat mezzanine board extends the PEXARIA5 board with I/Os. However, the WR1 connector on Black Cat is no longer used, as the W...
TimingSystemDocumentsCabeling
White Rabbit Cabling on the GSI/FAIR Campus Cable Specifications * Fiber Optic ITU T G.652 c or d * Wavelength transmission/reception 1490nm/1310nm *...
TimingSystemDocumentsConnectionEELabor
Connection to EE Labor This is just a temporary document, to be replaced by some proper documentation. Note on calculating cable lengths The cable length has bee...
TimingSystemDocumentsDBACCDBU
Network Equipment under the Responsibility of CSCOTG Cables, equipment and White Rabbit Switches are maintained using a database. Simple Viewer A simple viewer c...
TimingSystemDocumentsFTRNFeatures
Feature List for Timing Receivers at GSI and FAIR This page lists some hardware features for timing receivers at GSI and FAIR. Some recommended features will beco...
TimingSystemDocumentsGateFirmWare
Gateware and Firmware Gateware and firmware are provided with releases. * Gateware: synthesized (V)HDL code * Firmware: compiled code for the lm32 soft CPU ...
TimingSystemDocumentsMaster
The FAIR Timing Master in the "Betriebsgebäude" BG This is a collection of documents related to the FAIR Timing Master in the "Elektronikraum". Equipment Rack5...
TimingSystemDocumentsNetwork
Timing Network Introduction There are several instances of timing networks on the campus. * Productive * production: everything starting with the end of...
TimingSystemDocumentsPEXARIA5DB1
PEXARIA5DB The PEXIARA5DB is a mezzanine card for a PEXARIA5 carrier board. It exists in two variants. * PEXARIA5DB1, with IDC connector for LVDS signals: sche...
TimingSystemDocumentsRep201607222
Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...
TimingSystemDocumentsRep20211222
Booster Test December 2021 TL;DR For 'booster mode': * timing the beam transfer from UNILAC to SIS18 works with ~98% efficiency, if rf conditioning at UNILAC ...
TimingSystemDocumentsReportsAndMeasurements
Reports and Measurements This page serves to collect reports and measurements on the GMT. Booster Test * Timing events during 1st Booster Mode Test (2021 12 1...
TimingSystemDocumentsSIXIO2
FMC Module SIXIO2 The FMC module SIXIO2 has been designed by Jan Hoffmann / EE. It's purpose is simple I/O. * Info by EE: Some figures and specs * Sixio2_SC...
TimingSystemDocumentsSaftlib
Simple API For Timing (SaftLib) Simple API For Timing (SAFT). The design and implementation of SaftLib is a major project. Introduction The key features SaftLib ...
TimingSystemDoomsdayRelease
Doomsday Release (DEPRECATED) Previous releases are Asterisk, Balloon and Cherry. This release is replaced by Enigma. New features and bug fixes in Doomsday Rel...
TimingSystemEBWireshark
How To: Etherbone with Wireshark Introduction Wireshark might be useful when you need to inspect Etherbone packages sent via Ethernet, see here. Here are a few h...
TimingSystemERelease
Enigma Release (DEPRECATED) Previous releases are Asterisk, Balloon, Cherry and Doomsday. This release has been replaced by release Fallout. New Features and Bu...
TimingSystemErrorMsg
Documentation of Data Master Error Messages Parser Errors caused by faulty schedule data If any of the following error messages are reported to you or appear in ...
NEW - 17 Feb 2021 - 13:55 by MathiasKreider
TimingSystemEtherbone
Etherbone Introduction The idea behind the EtherBone (EB) protocol is to extend the reach of the embedded Wishbone (WB) V4 System on a chip (SoC) bus system to r...
TimingSystemEvent
Timing Messages Format of a Timing Message Timing messages is a term describing the input to a Timing Receiver (TR) that possibly leads to generation of a so cal...
TimingSystemEventNumbers
Event Numbers Overview Event numbers serve as IDs for actions performed by the control system. Existing Facility Information about event numbers used by the ex...
Number of topics: 50
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   <li>%INCLUDE{"%TOPIC%" section="searchbyletterlink" letter="V"}%</li>
   <li>%INCLUDE{"%TOPIC%" section="searchbyletterlink" letter="W"}%</li>
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   <li>%INCLUDE{"%TOPIC%" section="searchbyletterlink" letter="Y"}%</li>
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</ul>
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Topic revision: r1 - 09 Jan 2009, ProjectContributor
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