Detailed topic list for Timing Web

Results from Timing web retrieved at 09:17 (GMT)

Bel_Project_Building
BEL projects building HOW TO THIS HOWTO IS DEPRECATED Prerequistes The following packages are required to build BEL projects: $ sudo apt get install build esse...
EXPLODER5A
Figure 1: A complete exploder5a module (top view). Main.AlexanderHahn 15 Jul 2015
FirmwareID
Main.MathiasKreider 07 May 2015 Getting Information about the Firmware on a device Firmware IDs The eb info tool was used to read out the build id ROM, providin...
r3 - 11 May 2015 - 09:06 by MathiasKreider
FlashingWithEthernetBlaster
How To: Configuring and using Altera Ethernet Blaster to flash DM PRO * Download current gateware archive, unpack * Start Quartus Prime v18.0 * From 'T...
NEW - 20 Sep 2019 - 09:37 by MathiasKreider
GSITimingTeam
FAIR Timing/GSI Timing Team Core members of the GSI Timing Team are: T.Fleck C.Prados S.Rauch M.Kreider Further leading actors within the GSI controls group are U...
r3 - 05 Mar 2009 - 07:55 by TiborFleck
HdlmakeUbuntuInstall
hdlmake auf ein Ubuntu System installieren (Deprecated) THIS HOWTO IS DEPRECATED hdlmake ist ein Präprozessor um VHDL include files und VHDL source files in die...
Members
GSI Timing Team Core members of the GSI Timing Team are: F. Ameil (associated): work package lead (FAIR) D. Beck: some tools and docs, synchronization with UNILAC...
NetworkTopologyInterfaces
* chap2.pdf: Chapter2 Topology Main.CesarPrados 03 Mar 2009
r2 - 04 Mar 2009 - 13:52 by TiborFleck
ProgramPexaria5
Programmieren einer Pexaria 5 THIS HOWTO IS DEPRECATED Voraussetzungen : * USB Blaster * Promo 5 * 12 V Netzteil * Pexaria 5 * Quartus II Subscri...
Quartus16InstallMint191
Installing Quartus 18.1 on Linux Mint 19.2 Introduction Below steps are described to solve some trouble during and after installation of Quartus Prime Standard ...
QuartusInstallUbuntu1404
Installing Quartus under Ubuntu 14.04 (and possibly others) THIS HOWTO IS DEPRECATED Introduction This page contains a few notes on installing Altera's Quartu...
QuartusUbuntuInstallieren
Installieren Quartus II auf ein Ubuntu System: THIS HOWTO IS DEPRECATED * Download Quartus von https://www.altera.com/download/sw/dnl sw index.jsp * Quart...
Saftlib2MigrationGuide
Main.MichaelReese 07 Feb 2019 In response to user requests for lower latency communication and fewer library dependencies in saftlib, API breaking changes are int...
r30 - 12 Nov 2019 - 08:42 by MichaelReese
SaftlibEtherboneLm32LatencyMeasurement
MSI/IRQ Latency Measurements with LM32, Etherbone and Saftlib In autumn 2017, the latency of Message Signalled Interrupts (MSI) has been measured involving differ...
r5 - 30 Nov 2017 - 14:24 by MichaelReese
TimingSystemAMCTestingAndCommissioning
AMC Testing and Commissioning Guide Required components for each uTCA device * SFP (green/purple) * LC cable and a white rabbit switch (Recommended: RUN...
TimingSystemAcronyms
Acronyms These acronyms are focused on the timing system, but may contain other acronyms of the accelerator complex as well. Unclear Acronyms acronyms to be clar...
r9 - 19 Sep 2016 - 15:45 by MichaelReese
TimingSystemBallonRelease
Balloon Release (OUTDATED) The Balloon Release is NOT COMPATIBLE with the snapshot "January 2016" or previous releases or snapshots. If you want to test or integr...
TimingSystemBuTiSReceiver
BuTiS Receiver Station The BuTiS receiver station are maintained by the RF group, contact persons are P. Moritz or B. Zipfel. Setup Figure 1: BuTiS receiver sta...
TimingSystemButisInterface
White Rabbit, BuTiS, Clocks and Time Introduction Two systems exist for distribution of time stamps and clocks: 1. The General Machine Timing System provides ...
TimingSystemCherryRelease
Cherry Release V4 (OUTDATED) The Cherry Release is partly compatible with the the Balloon release. * ECA et al should be compatible * But ... * there ...
TimingSystemClockMaster
Clock Master Production This page documents the configuration of the Clock Master. Please note the corresponding How To. Introduction The Clock Master is the sou...
TimingSystemClockMasterOther
Clock Master Other This page documents the configuration of the Clock Master for the other White Rabbit networks (not 'Production'). Introduction The Clock Mast...
TimingSystemContext
The Timing System and its Context in the Accelerator Control System What is described here has been compiled from the Common Specifications for the Accelerator Co...
TimingSystemDBusInfo
Main.MichaelReese 30 Sep 2016 Saftlib is constructed around the DBus IPC system. In order to maintain and develop the library, a fairly good understanding of the ...
r16 - 15 Sep 2017 - 09:10 by MichaelReese
TimingSystemDMUniPZ
Gateway Data Master UNILAC PZ (dm unipz) Introduction "dm unipz" is the interface between the White Rabbit based Data Master und the MIL based UNILAC 'Pulszentr...
TimingSystemDataMaster
Data Master Configuration This page documents the configuration of the Data Master of the GMT for members of CSCOTG DM Technote: DM Manual. A DM Firmware and API ...
r22 - 14 Feb 2020 - 08:51 by MathiasKreider
TimingSystemDataMasterXMLFormat
The XML Format Used by the Data Master The DM uses an XML format to describe a schedule. Presently (09/2014), this format depends on implementation details. A (no...
TimingSystemDeprecatedDocumentation
Deprecated Documents This is just a unrevised collection of outdated or deprecated documents. * Feature List for a Timing Receiver Node at GSI/FAIR (09/2014)...
TimingSystemDeprecatedHowTo
Deprecated HOW TOs This is just a unrevised collection of outdated or deprecated HOW TOs. Timing Receivers * Building and Installation * HOW TO: Instal...
TimingSystemDocumentRep20180131
Etherbone Performance Measurements Introduction Access to Wishbone (WB) slaves in the FPGA from the host system is a prominent use case for the accelerator contr...
TimingSystemDocumentRep20180904
SCU Kernel Task Switching Latency Introduction The hardware group (thx to Stefan!) has investigated task switchting / preemption on the SCU kernel with RT patch ...
TimingSystemDocumentRep20190221
Pseudo SRAM Access from lm32 Introduction The W968D6DA provides 256Mbit (32MByte) of Pseudo SRAM (datasheet). It provides 32 bit address width and 16 data lines....
TimingSystemDocumentRep20190911
WR ZEN aka SSK Introduction The timing team (TOS) operates a couple of distinct White Rabbit networks. The most important one is a network called production, tha...
TimingSystemDocumentRep20191010
Report: Latency and Loss of Timing Messages in the Timing System Introduction Starting in October 2019 the ECA Tap module was added to the gateware of a few dedi...
TimingSystemDocumentation
Documentation Some documentation is given here. This is not structured but just a collection of various things. * Documents * HOW TOs * Releases * Cur...
TimingSystemDocuments
Documents Table of Contents Technical Documents General Machine Timing System * Timing System @ GSI * Master (10/2019) * Network (04/2015) ...
TimingSystemDocumentsAddOnBoardFeatures
Feature List for Add On boards of Timing Receivers at GSI and FAIR This page lists some hardware features for add on boards. Such add on boards are mezzanine boar...
TimingSystemDocumentsBlackCat1
Black_Cat1 Mezzanine Board The Black Cat mezzanine board extends the PEXARIA5 board with I/Os. However, the WR1 connector on Black Cat is no longer used, as the W...
TimingSystemDocumentsCabeling
White Rabbit Cabling on the GSI/FAIR Campus Cable Specifications * Fiber Optic ITU T G.652 c or d * Wavelength transmission/reception 1490nm/1310nm *...
TimingSystemDocumentsConnectionEELabor
Connection to EE Labor This is just a temporary document, to be replaced by some proper documentation. Note on calculating cable lengths The cable length has bee...
TimingSystemDocumentsDBACCDBU
Network Equipment under the Responsibility of CSCOTG Cables, equipment and White Rabbit Switches are maintained using a database. Simple Viewer A simple viewer c...
TimingSystemDocumentsFTRNFeatures
Feature List for Timing Receivers at GSI and FAIR This page lists some hardware features for timing receivers at GSI and FAIR. Some recommended features will beco...
TimingSystemDocumentsGateFirmWare
Gateware and Firmware Gateware and firmware are provided with releases, sometimes also referred to as GSI Timing Starter Kit. Around September 2012, the GSI Timin...
TimingSystemDocumentsMaster
The FAIR Timing Master in the "Betriebsgebäude" BG This is a collection of documents related to the FAIR Timing Master in the "Elektronikraum". Equipment Rack5...
TimingSystemDocumentsNetwork
Timing Network Introduction There are several instances of timing networks on the campus. * production: Strictly reserved for specific machines. Presently (sp...
TimingSystemDocumentsPEXARIA5DB1
PEXARIA5DB The PEXIARA5DB is a mezzanine card for a PEXARIA5 carrier board. It exists in two variants. * PEXARIA5DB1, with IDC connector for LVDS signals: sche...
TimingSystemDocumentsRep201607222
Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...
TimingSystemDocumentsReportsAndMeasurements
Reports and Measurements This page serves to collect reports and measurements on the GMT. Timing Receivers * saftlib * Saftlib 2.0 latency improvement (...
TimingSystemDocumentsSIXIO2
FMC Module SIXIO2 The FMC module SIXIO2 has been designed by Jan Hoffmann / EE. It's purpose is simple I/O. * Info by EE: Some figures and specs * Sixio2_SC...
TimingSystemDocumentsSaftlib
Simple API For Timing (SaftLib) Simple API For Timing (SAFT). The design and implementation of SaftLib is a major project. Introduction The key features SaftLib ...
Number of topics: 50
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Topic revision: r1 - 09 Jan 2009, ProjectContributor
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