200 recent changes in Timing Web retrieved at 22:25 (GMT)

TimingSystemDataMasterTestSystem
Documentation Data Master Test System Martin Skorsky Last change: 2021 07 22 * Hardware * SuperMicro fel0069 * White Rabbit Switch nwt0473m66 * ...
TimingSystemDataMaster
Data Master Manuals DM Technote: DM Manual. A DM Firmware and API Documentation. WIP, about 80% complete. Still trying to keep up with all the implemented feature...
TimingSystemEventNumbers
Event Numbers Overview Event numbers serve as IDs for actions performed by the control system. Existing Facility Information about event numbers used by the ex...
TimingSystemGroupsAndMachines
Groups and Machines Figure: Overview on GSI accelerators. Click here for a larger image. Overview Accelerator equipment relevant for the control system is organi...
TimingSystemFRelease
Fallout Release Previous releases are Asterisk, Balloon, Cherry, Doomsday and Enigma New features and bug fixes in Fallout Release * 2020 Aug 31: v6.0.0 alph...
WebHome
General Machine Timing System at GSI and FAIR The FAIR facility involves a long chain of accelerators which need to be tightly synchronized. This is achieved by t...
TimingSystemHowBuildingDeployment
How To: Building and Deployment for Linux Boxes and SCU Most of the code has been developed in the context of the White Rabbit Project and is hosted by the Open H...
TimingSystemDocumentsSaftlib
Simple API For Timing (SaftLib) Simple API For Timing (SAFT). The design and implementation of SaftLib is a major project. Introduction The key features SaftLib ...
r29 - 10 Jun 2021 - 12:07 by MichaelReese
TimingSystemHowConfigureWRMILGW
WR MIL gateway Introduction WR MIL gateways are a replacement for the existing SIS and ESR Pulszentrale (PZ). They are implemented in software running on a LM32 s...
r27 - 08 Jun 2021 - 10:00 by MichaelReese
TimingSystemHowTo
HOW TOs This is just a unrevised collection. The purpose is to write down some things, before we forget them... Timing System The recommended official interface ...
TimingSystemDocuments
Documents Table of Contents Technical Documents General Machine Timing System * Timing System @ GSI * Master (10/2019) * Network (04/2015) ...
TimingSystemHowPhtif
How To: Poor Humans TIF An Ugly Temporary TIF Workaround for the 2021 Beam Time Introduction As there is currently no replacement for the MIL TIFs with the new...
TimingSystemPEXPTestingAndCommissioning
PEXP Testing and Commissioning Guide Attention: This guide does not check the whole PCIe standard! Attention: This is NOT for FAT Required component...
TimingSystemDocumentRep20210218
Saftlib Latency Measurements During the startup of the accelerator in February 2021, issues have been observed with the so called function generator (FG): Occasio...
TimingSystemDocumentsReportsAndMeasurements
Reports and Measurements This page serves to collect reports and measurements on the GMT. Timing Receivers * saftlib * Saftlib latency; including fallou...
TimingSystemDiagnostics
Reading the DM status To get an overview on whats running on a DM, you can get the basic status by issuing root@tsl017 ~ # dm cmd dev/wbm0 or root@tsl017 ~ # dm...
NEW - 17 Feb 2021 - 15:29 by MathiasKreider
TimingSystemErrorMsg
Documentation of Data Master Error Messages Parser Errors caused by faulty schedule data If any of the following error messages are reported to you or appear in ...
NEW - 17 Feb 2021 - 13:55 by MathiasKreider
TimingSystemHowWebMonitoring
How To: Monitoring via Web Pages Introduction This How To describes how to do monitoring via web pages. Access Some web pages are only accessible on the GSI c...
TimingSystemHowToVersand
Sending Stuff from GSI Elsewhere THIS HOWTO IS DEPRECATED Requirements * ebiss Account @ GSI, see here * Account number ("Kostenstelle" or "Auftragsnumme...
TimingSystemTMIS
How To: TMIS Introduction TMIS (Timing Message Information Service) is a quick evaluation on distribution of timing messages via the ACC controls network. The ma...
Members
GSI Timing Team Core members of the GSI Timing Team are: F. Ameil (associated): work package lead (FAIR) D. Beck: operation, tools and docs, legacy stuff for UNIL...
TimingSystemOlderNews
Older News * 23 Dec 2020: ad hoc maintenance timing system (White Rabbit @ UNILAC only) * WRS memory leak: bug found and fixed, new WRS firmware availabl...
TimingSystemHowEventSnoopTool
Timing Messages: How To Snoop the Timing System News FEC for FESA class is now scuxl0143. Introduction This is a first simple solution to view what is going on ...
FlashingWithEthernetBlaster
How To: Configuring and using Altera Ethernet Blaster to flash DM PRO * Download current gateware archive, unpack * Copy jic file to tmp directory on tsl021...
r2 - 22 Jan 2021 - 09:50 by MathiasKreider
TimingSystemHowConfigureDMUniPZ
How To: dm unipz Hinweise * Eine aktuelle Version dieses Dokumentes ist via https://www acc.gsi.de/wiki/Timing/TimingSystemHowConfigureDMUniPZ verfuegbar. *...
TimingSystemHowPCSetup
How To: Setting Up a Linux Box Intended usage: E Release For older releases please check out the history of this Wiki page. Introduction This how to describes se...
TimingSystemHowSaftCtl
How To: saft ctl Introduction This tool is intended to diagnose the status saftlib and provide ECA related information of a timing receiver. Moreover one can do ...
r5 - 10 Dec 2020 - 11:03 by MichaelReese
TimingSystemHowSaftDm
How To: saft dm Introduction This tool (saft dm: "saft Data Master") is intended to provide a primitive Data Master for local operations in the FEC. This tool mi...
r3 - 10 Dec 2020 - 11:00 by MichaelReese
TimingSystemMacAuthentication
White Rabbit Switch 802.1X MAC Authentication Introduction This is a standard feature of 'normal' network switches from Cisco, HP, ... and involves a remote Radi...
TimingSystemButisInterface
White Rabbit, BuTiS, Clocks and Time Introduction Two systems exist for distribution of time stamps and clocks: 1. The General Machine Timing System provides ...
TimingSystemHowFlashFTRNUser
How To: Flash a Timing Receiver with a Gateware/Firmware Image Introduction This how to is intended for non experts and describes how to flash a timing receiver ...
WebNotify
* .AndreasReiter: * * .DietrichBeck: * * .HaraldBraeuning: * * .MichaelReese: * .RalphBaer: * * .NikolausKurz: * * .WikiGuest * .WikiGuest ...
TimingSystemNodesCurrentRelease
This pages just includes the page of the current release. For editing that page, go here.
TimingSystemPexaria5TestingAndCommissioning
Testing and Commissioning Guide for Pexaria5 Required components * Pexaria5 under test (named as P5UT in this guide) * PC with Intel Quartus (version 18...
NEW - 07 Oct 2020 - 09:56 by EnkhboldOchirsuren
TimingSystemERelease
Enigma Release (DEPRECATED) Previous releases are Asterisk, Balloon, Cherry and Doomsday. This release has been replaced by release Fallout. New Features and Bu...
TimingSystemDocumentsGateFirmWare
Gateware and Firmware Gateware and firmware are provided with releases. * Gateware: synthesized (V)HDL code * Firmware: compiled code for the lm32 soft CPU ...
TimingSystemRelease
Releases and Snapshots of the Timing System Release A Timing Firmware Release packs together new features and requirements defined in our Development Road Map, ...
TimingSystemHowSaftIoCtl
How To: saft io ctl Introduction Use this tool to configure I/Os and setup rules for I/Os in the ECA. Usage IO CTL for SAFTlib Usage: saft io ctl OPTIONS Ar...
TimingSystemHowTRRegistration
How To: Connecting a Timing Receiver to the White Rabbit Network A timing receiver MUST NOT be connected to a White Rabbit network without authorization. Authori...
TimingSystemHowConfigureWRUniPZ
How To: White Rabbbit UNILAC PZ (wr unipz) Betrieb Hinweis: Eine aktuelle Version dieses Dokumentes ist via https://www acc.gsi.de/wiki/Timing/TimingSystemHowCo...
TimingSystemHowSoftCPUCompiler
How To: LM32 Soft CPU Compiler Introduction This how to describes the status and how to build the compiler for the lm32 soft cpu. Links * on github (for be...
TimingSystemHowDevAcc
How To: Poor Man's (d, m, w) Path to Device Access Introduction This How To is not even a how to. Instead, it is just a collection of stuff required to develop a...
TimingSystemHowWRUniPZ
Introduction "wr unipz" is a component of the MIL based UNILAC 'Pulszentrale' (UNIPZ). As a field bus, it does not use the MIL 'Event' bus but a White Rabbit netw...
TimingSystemHowSaftUni
How To: saft uni Introduction This tool is intended to diagnose UNILAC operation. This tool is experimental! The standard tool saft ctl can of course be used. Ho...
TimingSystemEvent
Timing Messages Format of a Timing Message Timing messages is a term describing the input to a Timing Receiver (TR) that possibly leads to generation of a so cal...
TimingSystemWRUniPZ
White Rabbbit UNILAC PZ (wr unipz) UNIPZ Figure: Most simplified view on UNIPZ (upper part). It is a combination of a Super UNIPZ and seven UNIPZ1..7. Shown ...
TimingSystemWRSWitchNewHW
White Rabbit Switch Hardware 4.0 Overview This page summarizes the GSI requirements in context with the development of a new version of the White Rabbit Switch. ...
GHDLVHPI
GHDL coupling to C via VHPI Motivation It is often useful to call into c libraries from within a VHDL simulation/testbench * because VHDL standard library is ...
NEW - 24 Jun 2020 - 14:59 by MichaelReese
TimingSystemHowSaftLcd
How To: saft lcd Introduction This is a an experimental GSI specific command line tool for live display of Beam Production Chains (BPC). Usage via Command Line ...
TimingSystemHowCodeDeployWRUniPZ
How To: White Rabbbit UNILAC PZ (wr unipz) Coding and Deployment Stack of the White Rabbit Pulszentrale Figure: Overview on the White Rabbit Pulszentrale. Sh...
TimingSystemFrontendAccess
How To: Accessing ACO Frontends Using ACO Tools Introduction This how to is just intended as a primer for non specialists. Disclaimer: There are many, many possi...
TimingSystemGSTrUsage
Timing Receiver: Usage For using a Timing Receiver (TR) please follow the directions here. What is Needed * TR hardware, see here what is supported by the cur...
TimingSystemNetworkBasics
(Some) Basics of Networking and White Rabbit The prime source for information for White Rabbit project is the Open Hardware Repository. The aim of this page is to...
WebStatistics
Statistics for Timing Web Month: Topic views: Topic saves: File uploads: Most popular topic views: Top contributors for topic save and uploads: ...
TimingSystemHowSoftCPU
How To: LM32 Soft CPU Introduction Soft CPUs are a VDHL implementation of a CPU in a FPGA. With FAIR Timing Receivers, Soft CPUs are directly embedded in the Wis...
TimingSystemDocumentRep20191010
Report: Latency and Loss of Timing Messages in the Timing System Introduction Starting in October 2019 the ECA Tap module was added to the gateware of a few dedi...
TimingSystemAMCTestingAndCommissioning
AMC Testing and Commissioning Guide Required components for each uTCA device * SFP (green/purple) * LC cable and a white rabbit switch (Recommended: RUN...
TimingSystemHowQuickStart
How To: Quick Start THIS HOWTO IS DEPRECATED (look in the /bel_projects readme) The following will provide you with "master" of our our repository. 1 git clo...
r6 - 03 Dec 2019 - 14:53 by MarcusZweig
TimingSystemPolicies
Policies in the Timing Network * The timing network is managed by TOS and TOS defines the policies. * The timing network is a "field bus" synchronizing the...
TimingSystemDoomsdayRelease
Doomsday Release (DEPRECATED) Previous releases are Asterisk, Balloon and Cherry. This release is replaced by Enigma. New features and bug fixes in Doomsday Rel...
TimingSystemEtherbone
Etherbone Introduction The idea behind the EtherBone (EB) protocol is to extend the reach of the embedded Wishbone (WB) V4 System on a chip (SoC) bus system to r...
Saftlib2MigrationGuide
Main.MichaelReese 07 Feb 2019 In response to user requests for lower latency communication and fewer library dependencies in saftlib, API breaking changes are int...
r30 - 12 Nov 2019 - 08:42 by MichaelReese
TimingSystemHowConfigureFTRNCommandLine
How To: Command Line Tools for Timing Receiver (including SCU) Introduction A set of command line tools is deployed and available on Front End Computers (FECs). ...
Quartus16InstallMint191
Installing Quartus 18.1 on Linux Mint 19.2 Introduction Below steps are described to solve some trouble during and after installation of Quartus Prime Standard ...
TimingSystemClockMasterOther
Clock Master Other This page documents the configuration of the Clock Master for the other White Rabbit networks (not 'Production'). Introduction The Clock Mast...
TimingSystemDocumentsMaster
The FAIR Timing Master in the "Betriebsgebäude" BG This is a collection of documents related to the FAIR Timing Master in the "Elektronikraum". Equipment Rack5...
TimingSystemClockMaster
Clock Master Production This page documents the configuration of the Clock Master. Please note the corresponding How To. Introduction The Clock Master is the sou...
TimingSystemHowEbMon
How To: eb mon Introduction The original intention about this tool has been to get (simpler) access to data of the White Rabbit PTP core. But as the name suggest...
TimingSystemEBWireshark
How To: Etherbone with Wireshark Introduction Wireshark might be useful when you need to inspect Etherbone packages sent via Ethernet, see here. Here are a few h...
TimingSystemHowGenerateBursts
Main.EnkhboldOchirsuren 14 Aug 2019 How To: Burst generation this functionality is under development and not available in any release A simple solution for gener...
r9 - 20 Sep 2019 - 12:57 by EnkhboldOchirsuren
TimingSystemDocumentRep20190911
WR ZEN aka SSK Introduction The timing team (TOS) operates a couple of distinct White Rabbit networks. The most important one is a network called production, tha...
TimingSystemNodesReleaseAsteriskExploder5aCommission
Exploder5a Commissioning Guide Note: This test is functional. It is not intended to cover verification validation tests of the design! Note: Software/Version ...
r25 - 06 Sep 2019 - 14:04 by EnkhboldOchirsuren
TimingSystemHowSnoopy
How To: snoopy spy Introduction This is a simple command line tool and provided by one of our colleagues from FEC and available on the ASL 7 cluster. Altho...
TimingSystemCherryRelease
Cherry Release V4 (OUTDATED) The Cherry Release is partly compatible with the the Balloon release. * ECA et al should be compatible * But ... * there ...
TimingSystemBallonRelease
Balloon Release (OUTDATED) The Balloon Release is NOT COMPATIBLE with the snapshot "January 2016" or previous releases or snapshots. If you want to test or integr...
TimingSystemNodesReleaseAsterisk
Release Asterisk v2 (for miniCS) and updates compatible with SaftLib ( OUTDATED ) Asterisk is compatible to the control system releases R3, R4, R5 and R6 The rele...
TimingSystemHowSoftCPUStackCheck
How To: LM32 Soft CPU Simple Stack Check Introduction This how to demonstrates how a simple check for possible stack violation has been implemented. Principle...
TimingSystemDeprecatedHowTo
Deprecated HOW TOs This is just a unrevised collection of outdated or deprecated HOW TOs. Timing Receivers * Building and Installation * HOW TO: Instal...
QuartusInstallUbuntu1404
Installing Quartus under Ubuntu 14.04 (and possibly others) THIS HOWTO IS DEPRECATED Introduction This page contains a few notes on installing Altera's Quartu...
TimingSystemHowConfigureEnvironment
Ohps! You are looking for an old wiki page that has been renamed. Try this wiki page Main.DietrichBeck 19 Jun 2019
TimingSystemNodesSnapshotJan2016
Snapshot "January 2016" The intention of this snapshot is twofold. First, to make improvement of White Rabbit available at GSI. Second, to provide again a consist...
TimingSystemHowEbFwload
How To: eb fwload Introduction This tool has been written to ease software development form lm32 Soft Cores. It allows to upload firmware to one or more Soft Cor...
TimingSystemHowInstallFTRN
How To: Installation of a Timing Receiver THIS HOWTO IS DEPRECATED Introduction Installation of a timing receivers should be easy and straight forward. The phy...
TimingSystemHowTriggerLM32FromEca
Timing Messages: How To test the ECA queue from LM32 Soft CPU and PC Introduction The specified ECA queue is used to storage timing events filtered by eventID. T...
TimingSystemHowtoRTE
How to Build and Deploy the Timing Run Time Environment THIS HOWTO IS DEPRECATED The documentation here describes a version of the script that has never been pu...
TimingSystemHowtoRTEManual
Building and Deployment for a Specific Kernel and Installation into a Staging Directory THIS HOWTO IS DEPRECATED Remark: This is really special. The information...
TimingSystemSwitchHowToDIM
WR Switch: How To Cross Compile DIM THIS HOWTO IS DEPRECATED This describes the first try to cross compile DIM for a White Rabbit switch. DIM is a communication...
TimingSystemSwitchRemoteMonitoring
WR Switch: Basic Remote Monitoring (Deprecated) THIS HOWTO IS DEPRECATED This describes how basic remote monitoring of White Rabbit switches can be done by usin...
TimingSystemSwitchHowToHelloWorld
WR Switch: How To Cross Compile Hello World THIS HOWTO IS DEPRECATED This describes how I cross compiled hello world for switch Getting the Tools This assumes ...
TimingSystemSwitchHowToUsing
WR Switch: How To Use a WR Switch THIS HOWTO IS DEPRECATED This is just a short list of things I found useful Login to a Switch * ssh via the management po...
TimingSystemSwitchHowToFlash
WR Switch: How To Flash a WR Switch THIS HOWTO IS DEPRECATED Introduction Most importantly, you should the WRS manual. For version 4.2, see here. Basically, al...
HdlmakeUbuntuInstall
hdlmake auf ein Ubuntu System installieren (Deprecated) THIS HOWTO IS DEPRECATED hdlmake ist ein Präprozessor um VHDL include files und VHDL source files in die...
QuartusUbuntuInstallieren
Installieren Quartus II auf ein Ubuntu System: THIS HOWTO IS DEPRECATED * Download Quartus von https://www.altera.com/download/sw/dnl sw index.jsp * Quart...
TimingSystemHowToMiniCS
Timing System within miniCS THIS HOWTO IS DEPRECATED After reflashing and upgrading the SCUs to 64bit, the timing system of release R1 is no longer operational!...
TimingSystemHowToHelloWorldSoftCPU
Hello World on lm32 Soft CPU THIS HOWTO IS DEPRECATED A soft CPU based on the lm32 is embedded in the White Rabbit core. This how to describes a "Hello World" f...
TimingSystemHowToInstallSoftCPUforPEXARIA2A
Installation of Tool Chain for the lm32 Soft CPU THIS HOWTO IS DEPRECATED A soft CPU based on the lm32 is embedded in the White Rabbit core. This how to describ...
TimingSystemHowToInstallSoftCPUforSPECV2
Tool Chain for a SPEC Board. THIS HOWTO IS DEPRECATED A soft CPU based on the lm32 is embedded in the White Rabbit core. This how to describes the installation ...
TimingSystemHowConfigureFTRNVME
FAIR Timing Receiver Node: How To Configure and Operate a VME Timing Receiver (outdated) THIS HOWTO IS DEPRECATED August 2013 Introduction The VETAR2 is the ne...
ProgramPexaria5
Programmieren einer Pexaria 5 THIS HOWTO IS DEPRECATED Voraussetzungen : * USB Blaster * Promo 5 * 12 V Netzteil * Pexaria 5 * Quartus II Subscri...
TimingSystemHowTRInstallation
How To: Installation of a Timing Receiver or SCU THIS HOWTO IS DEPRECATED This how to summarizes the steps required to install a timing receiver. Setup up a FE...
Bel_Project_Building
BEL projects building HOW TO THIS HOWTO IS DEPRECATED Prerequistes The following packages are required to build BEL projects: $ sudo apt get install build esse...
TimingSystemHowEbInfo
How To: eb info Introduction This tool has been written to get information on gateware and firmware actually employed. Usage Usage: eb info OPTION w ...
TimingSystemHowSoftCPUHandleECAMSIs
How To: LM32 Soft CPU Handle the ECA message signaled interrupts (MSIs) Introduction The ECA unit is capable to send MSI on certain conditions, such as: * p...
TimingSystemVetar2aDirectAccessMode
Main.MichaelReese 22 Aug 2017 Vetar2a: VME WB bridge direct access mode The normal mode of operation (after reset) of the Vetar2a card uses a VME wishbone bridge...
r7 - 11 Apr 2019 - 09:35 by MichaelReese
TimingSystemPMCTestingAndCommissioning
PMC Testing and Commissioning Guide Attention: This guide does not check the whole PCI/PMC standard! Attention: This is NOT for FAT Required comp...
TimingSystemDocumentRep20190221
Pseudo SRAM Access from lm32 Introduction The W968D6DA provides 256Mbit (32MByte) of Pseudo SRAM (datasheet). It provides 32 bit address width and 16 data lines....
TimingSystemContext
The Timing System and its Context in the Accelerator Control System What is described here has been compiled from the Common Specifications for the Accelerator Co...
TimingSystemDocumentRep20180131
Etherbone Performance Measurements Introduction Access to Wishbone (WB) slaves in the FPGA from the host system is a prominent use case for the accelerator contr...
TimingSystemDeprecatedDocumentation
Deprecated Documents This is just a unrevised collection of outdated or deprecated documents. * Feature List for a Timing Receiver Node at GSI/FAIR (09/2014)...
TimingSystemDocumentation
Documentation Some documentation is given here. This is not structured but just a collection of various things. * Documents * HOW TOs * Releases * Cur...
TimingSystemGSEca
Timing Receiver: Event Condition Action Unit Figure: A Timing Receiver embedded in a Front End Computer. The core component is the Event Condition Action unit (...
TimingSystemGettingStarted
Getting Started * Essentials * Timing Receiver: Event Condition Action Unit * Timing Receiver: Usage Main.DietrichBeck 16 Nov 2018
TimingSystemGSOverview
Essentials Figure: Building blocks required for a single 'timing event' Bang!. Components of the General Machine Timing (GMT) are shown in blue. Components requ...
TimingSystemOverview
Introduction to the General Machine Timing System The FAIR facility involves a long chain of accelerators which need to be tightly synchronized. An important cons...
TimingSystemDocumentRep20180904
SCU Kernel Task Switching Latency Introduction The hardware group (thx to Stefan!) has investigated task switchting / preemption on the SCU kernel with RT patch ...
TimingSystemHowFECCheck
How To: Check a FEC Introduction This How To describes how to check a FEC works properly with respect to features provided by the GMT. Test Plan This is just a ...
TimingSystemDMUniPZ
Gateway Data Master UNILAC PZ (dm unipz) Introduction "dm unipz" is the interface between the White Rabbit based Data Master und the MIL based UNILAC 'Pulszentr...
TimingSystemHowEbReset
How To: eb rest Introduction This tool has been written to easy 'reset of FPGA'. This cycles the FPGA and (re)loads the image from the flash to the FPGA. Use too...
TimingSystemFEC
How To: WB_FEC This wiki provides information about * WB FEC VHDL module and integration in Bel_Projects * Synthesis of Timing Receiver Gateware with the WB...
TimingSystemHowConfigureDataMaster
Data Master: How To Configure and Operate There are different versions of the data master depending on the release of the control system. * Release R12 "Cherr...
r9 - 12 Mar 2018 - 09:57 by MathiasKreider
TimingSystemNextReleaseCandidate
"D?" Candidate Release Probably in March 2018. See here. Main.DietrichBeck 01 Mar 2018
TimingSystemPCIeDirectAccessMode
Main.MichaelReese 15 Feb 2018 this is an experimental feature that is not part of any release yet PCIe WB bridge direct access mode PCIe timing hardware where th...
r5 - 16 Feb 2018 - 14:36 by MichaelReese
TimingSystemDocumentsRep201607222
Torture Report about GMT with Debian on PC and SL6/CentOS 7 on SCU3 Setup A schedule containing three messages is iterated by the Data Master. The messages are s...
WRSimulation
WR Simulation How To This How To guide you in the simulation of the WR Core and WR Switch. Setup the Simulation environment You need a ModelSim runnig in your sy...
r5 - 24 Jan 2018 - 15:40 by cprados
TimingSystemHowOperateClockMaster
Clock Master: How To Operate Introduction This How To is intended for the members of the timing team. The clock master is the White Rabbit Grandmaster Clock of t...
TimingSystemHowConfigureDataMasterR11
Data Master: How To Configure and Operate for Release R11 ("Cherry") Introduction This How To is intended for the members of the timing team. The data master is ...
TimingSystemNodesReleaseAsteriskPexaria5Commission
Step by step guide to commissioning a new pexaria5: 1 Place powered off pexaria5 on ESD desk , ESD dischare! 1 Attach wrex2a addon board to baseboard WR1 (W...
TimingSystemHowConfigureDataMasterR3
Data Master: How To Configure and Operate for Release R3 R9 ("Balloon") DEPRECATED Introduction This How To is intended for the members of the timing team. The d...
TimingSystemHowConfigureDataMasterR10
Data Master: How To Configure and Operate for Release R10 ("Pre Cherry") DEPRECATED Introduction This How To is intended for the members of the timing team. The...
SaftlibEtherboneLm32LatencyMeasurement
MSI/IRQ Latency Measurements with LM32, Etherbone and Saftlib In autumn 2017, the latency of Message Signalled Interrupts (MSI) has been measured involving differ...
r5 - 30 Nov 2017 - 14:24 by MichaelReese
Wrlldp
How To: WR LLDP This how to describes how to use LLDP in WR Devices. It is not meant to clarify what is LLDP. Info (November 2017): The development is already in...
TimingSystemGPSDO
GPSDO The GPSDO serves as a primary reference time source for the timing system. Amongst the interfaces, there are three Gigabit Ethernet ports for NTP servers. ...
TimingSystemDBusInfo
Main.MichaelReese 30 Sep 2016 Saftlib is constructed around the DBus IPC system. In order to maintain and develop the library, a fairly good understanding of the ...
r16 - 15 Sep 2017 - 09:10 by MichaelReese
TimingSystemNodesSnapshotApr2017
Snapshot April 2017 DON'T USE THIS SNAPSHOT!!! IT WAS DECIDED TO CANCEL THE ROLL OUT. This snapshot became necessary due to updates of the so called "function...
TimingSystemHowSoftCPULM32Command
How To: LM32 Soft CPU Send a Command to a LM32 Soft CPU Introduction This how to demonstrates how to send a command to LM32 Soft CPU. This how to demonstrates ...
TimingSystemHowSoftCPUUseDevicebus
How To: LM32 Soft CPU Using MIL Devicebus Introduction This how to demonstrates how to access a device on a MIL Devicebus connected to the SCU ("MIL piggy"). A...
TimingSystemHowSoftCPUAccessLM32SharedMemWB
How To: LM32 Soft CPU Accessing a LM32 Soft CPU via shared memory and Wishbone Introduction This how to demonstrates how to access the LM32 Soft CPU via Shared...
TimingSystemHowSoftCPUAccessOtherWB
How To: LM32 Soft CPU Accessing Another SoC Wishbone Device Introduction This how to demonstrates how to access another Wishbone device on the same SoC from th...
TimingSystemAcronyms
Acronyms These acronyms are focused on the timing system, but may contain other acronyms of the accelerator complex as well. Unclear Acronyms acronyms to be clar...
r9 - 19 Sep 2016 - 15:45 by MichaelReese
EXPLODER5A
Figure 1: A complete exploder5a module (top view). Main.AlexanderHahn 15 Jul 2015
TimingSystemNodesReleaseAsteriskVetar2aCommission
Vetar2a Commissioning Guide Note: This test is functional. It is not intended to cover verification validation tests of the design! Needed components for each...
TimingSystemIrradtionSIS18
Irradiation of Fibres at SIS18 Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be possible, that fibres to ...
FirmwareID
Main.MathiasKreider 07 May 2015 Getting Information about the Firmware on a device Firmware IDs The eb info tool was used to read out the build id ROM, providin...
r3 - 11 May 2015 - 09:06 by MathiasKreider
TimingSystemDocumentsNetwork
Timing Network Introduction There are several instances of timing networks on the campus. * production: Strictly reserved for specific machines. Presently (sp...
TimingSystemDocumentsCabeling
White Rabbit Cabling on the GSI/FAIR Campus Cable Specifications * Fiber Optic ITU T G.652 c or d * Wavelength transmission/reception 1490nm/1310nm *...
TimingSystemNodesReleaseR1VETAR2
VETAR2 (Release R1) The VETAR2 is a VME carrier board that can be White Rabbit enabled using the VETAR1DB2 add on board. I/Os are defined by a mezzanine board. H...
TimingSystemLSAInterface
FESA Properties for DataMaster Class (current version running on vmla03) Global Interface (Device Name MCS_DM_GLOBAL) Setting Properties * Command * dataM...
r10 - 22 Oct 2014 - 09:37 by MathiasKreider
TimingSystemDataMasterXMLFormat
The XML Format Used by the Data Master The DM uses an XML format to describe a schedule. Presently (09/2014), this format depends on implementation details. A (no...
TimingSystemDocumentsFTRNFeatures
Feature List for Timing Receivers at GSI and FAIR This page lists some hardware features for timing receivers at GSI and FAIR. Some recommended features will beco...
TimingSystemNodesReleaseR1Exploder2C
EXPLODER2C (Release R1) The EXPLODER2C is a carrier board for a stand alone device based on an ArriaII FGPA. It can be White Rabbit enabled using the WREX1 add on...
TimingSystemNodesReleaseR1
Nodes: Release R1 Overview rpd ...
TimingSystemNodesReleaseR1SCU2
SCU2 (Release R1) The SCU (Scalable Control Unit) is the standard front end controller used by the CSCO group based on an ArriaII FPGA. It can be White Rabbit ena...
TimingSystemNodesReleaseR1PEXARIA5
PEXARIA5 (Release R1) The PEXIARA5A is a PCIe carrier board based on an ArriaV FPGA. It can be White Rabbit enabled using a WREX1 add on board. I/O are implemente...
TimingSystemDocumentsBlackCat1
Black_Cat1 Mezzanine Board The Black Cat mezzanine board extends the PEXARIA5 board with I/Os. However, the WR1 connector on Black Cat is no longer used, as the W...
TimingSystemDocumentsSIXIO2
FMC Module SIXIO2 The FMC module SIXIO2 has been designed by Jan Hoffmann / EE. It's purpose is simple I/O. * Info by EE: Some figures and specs * Sixio2_SC...
TimingSystemBuTiSReceiver
BuTiS Receiver Station The BuTiS receiver station are maintained by the RF group, contact persons are P. Moritz or B. Zipfel. Setup Figure 1: BuTiS receiver sta...
TimingSystemManagementMaster
Management Master Configuration ... to be done... Main.DietrichBeck 03 Apr 2014
TimingSystemHowConfigureDataMasterR1
Data Master: How To Configure and Operate for Release R1 This describes the temporary solution derived from miniCS (July 2013). This information is outdated, as...
TimingSystemDocumentsPEXARIA5DB1
PEXARIA5DB The PEXIARA5DB is a mezzanine card for a PEXARIA5 carrier board. It exists in two variants. * PEXARIA5DB1, with IDC connector for LVDS signals: sche...
TimingSystemDocumentsDBACCDBU
Network Equipment under the Responsibility of CSCOTG Cables, equipment and White Rabbit Switches are maintained using a database. Simple Viewer A simple viewer c...
TimingSystemIrradtionHHD
Irradiation of Fibres at HHD Cave (SIS18 beam dump) Introduction For FAIR, timing sensitive equipment will be installed in the niches of SIS100. It might be poss...
TimingSystemDocumentsConnectionEELabor
Connection to EE Labor This is just a temporary document, to be replaced by some proper documentation. Note on calculating cable lengths The cable length has bee...
TimingSystemDocumentsAddOnBoardFeatures
Feature List for Add On boards of Timing Receivers at GSI and FAIR This page lists some hardware features for add on boards. Such add on boards are mezzanine boar...
WebPreferences
Timing Web Preferences Appearance * Set WEBBGCOLOR = #669966 * web specific background color, current color * Set SITEMAPLIST = on * set to...
GSITimingTeam
FAIR Timing/GSI Timing Team Core members of the GSI Timing Team are: T.Fleck C.Prados S.Rauch M.Kreider Further leading actors within the GSI controls group are U...
r3 - 05 Mar 2009 - 07:55 by TiborFleck
NetworkTopologyInterfaces
* chap2.pdf: Chapter2 Topology Main.CesarPrados 03 Mar 2009
r2 - 04 Mar 2009 - 13:52 by TiborFleck
WebAtom
Foswiki's Timing web
WebRss
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Topic revision: r1 - 09 Jan 2009, ProjectContributor
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