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The Timing System and its Context in the Accelerator Control System What is described here has been compiled from the Common Specifications for the Accelerator Co...
28 Jan 2019 - 12:45
The XML Format Used by the Data Master The DM uses an XML format to describe a schedule. Presently (09/2014), this format depends on implementation details. A (no...
29 Sep 2014 - 11:54
Documents Table of Contents Technical Documents General Machine Timing System * Timing System @ GSI * Master (10/2019) * Network (04/2015) ...
25 Aug 2021 - 12:46
Reports and Measurements This page serves to collect reports and measurements on the GMT. Timing Receivers * saftlib * Saftlib latency; including fallou...
18 Feb 2021 - 07:38
WR MIL gateway Introduction WR MIL gateways are a replacement for the existing SIS and ESR Pulszentrale (PZ). They are implemented in software running on a LM32 s...
08 Jun 2021 - 10:00
How To: Poor Humans TIF An Ugly Temporary TIF Workaround for the 2021 Beam Time Introduction As there is currently no replacement for the MIL TIFs with the new...
19 Apr 2021 - 15:22
How To: saft ctl Introduction This tool is intended to diagnose the status saftlib and provide ECA related information of a timing receiver. Moreover one can do ...
10 Dec 2020 - 11:03
Introduction "wr unipz" is a component of the MIL based UNILAC 'Pulszentrale' (UNIPZ). As a field bus, it does not use the MIL 'Event' bus but a White Rabbit netw...
01 Sep 2021 - 12:43
Older News * 23 Dec 2020: ad hoc maintenance timing system (White Rabbit @ UNILAC only) * WRS memory leak: bug found and fixed, new WRS firmware availabl...
24 Jan 2021 - 15:52
How To: TMIS Introduction TMIS (Timing Message Information Service) is a quick evaluation on distribution of timing messages via the ACC controls network. The ma...
25 Jan 2021 - 19:27
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