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TimingSystemContext
The Timing System and its Context in the Accelerator Control System What is described here has been compiled from the Common Specifications for the Accelerator Co...
TimingSystemDataMasterXMLFormat
The XML Format Used by the Data Master The DM uses an XML format to describe a schedule. Presently (09/2014), this format depends on implementation details. A (no...
TimingSystemDocuments
Documents Table of Contents Technical Documents General Machine Timing System * Timing System @ GSI * Master (10/2019) * Network (04/2015) ...
TimingSystemDocumentsReportsAndMeasurements
Reports and Measurements This page serves to collect reports and measurements on the GMT. Timing Receivers * saftlib * Saftlib latency; including fallou...
TimingSystemHowConfigureWRMILGW
WR MIL gateway Introduction WR MIL gateways are a replacement for the existing SIS and ESR Pulszentrale (PZ). They are implemented in software running on a LM32 s...
r27 - 08 Jun 2021 - 10:00 by MichaelReese
TimingSystemHowPhtif
How To: Poor Humans TIF An Ugly Temporary TIF Workaround for the 2021 Beam Time Introduction As there is currently no replacement for the MIL TIFs with the new...
TimingSystemHowSaftCtl
How To: saft ctl Introduction This tool is intended to diagnose the status saftlib and provide ECA related information of a timing receiver. Moreover one can do ...
r5 - 10 Dec 2020 - 11:03 by MichaelReese
TimingSystemHowWRUniPZ
Introduction "wr unipz" is a component of the MIL based UNILAC 'Pulszentrale' (UNIPZ). As a field bus, it does not use the MIL 'Event' bus but a White Rabbit netw...
TimingSystemOlderNews
Older News * 23 Dec 2020: ad hoc maintenance timing system (White Rabbit @ UNILAC only) * WRS memory leak: bug found and fixed, new WRS firmware availabl...
TimingSystemTMIS
How To: TMIS Introduction TMIS (Timing Message Information Service) is a quick evaluation on distribution of timing messages via the ACC controls network. The ma...
Number of topics: 10
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