Etherbone

Introduction

The idea behind the EtherBone (EB) protocol is to extend the reach of the embedded Wishbone (WB) V4 System-on-a-chip (SoC) bus system to remote field-programmable gate arrays or processors. The EtherBone core implementation connects a Wishbone bus via (typically) serial protocols such as Gigabit Ethernet, PCIe or USB to remote peripheral devices. EB acts as a transparent interconnect module towards attached WB Bus devices. EB was developed in the scope of the White Rabbit Timing Project at CERN and GSI/FAIR. White Rabbit will make use of EB as a means to issue commands to its timing nodes and control connected accelerator hardware.

etherboneStack.jpgFigure: Stack from a userland application on a host to a Wishbone device in the FPGA including EtherBone.

As shown in the figure above, Etherbone can be used via almost any serial protocol available. Examples are PCIe, USB, UDP and TCP; even parallel buses like PCI or VME are possible using dedicated drivers. NB: The WB architecture employed by White Rabbit nodes at CERN and GSI, makes use of the so-called Self-Describing Bus (SDB) that allows to enumerate the cores that are live in the current FPGA binary. Etherbone and SDB allow to inspect and communicate with Wishbone devices in the FPGA.

Further Details and Documentation

The best starting point is a Physical Review Special Topics edition, see here.

Command Line Tools

To get familiar with using Etherbone, try out the so-called EB tools that are available at the command line of a Timing Receivers host system.

Code Examples

  • C API is available here
  • a documented example is available here
  • have a look at the so-called "EB Tools" that are part of our current release.

Docs

-- DietrichBeck - 17 November 2018

This topic: Timing > WebHome > TimingSystemDocumentation > TimingSystemDocuments > TimingSystemEtherbone
Topic revision: 14 Nov 2019, MartinSkorsky
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