Injection-Kicker of SIS100

Attention:

Check if it makes sense to merge SIS1000 Injection with SIS100 Extraction Kicker class !!

Both kickers share the same Hardware, though SIS100 Extraction KIcker is a ramped device, where Injection kicker is not.

Possibly some PLC settings differ ?

General

  • Kicker consistst of six independent modules.
  • kicker will be non-ramped

Software Modellation:
  • P. Spiller requests (mail to D. Ondreka, R. Bär et al from 05-Jul-2010): each of the 6 kicker module must be modelled as independent device, not combined to a resulting kicker (as is done in SIS18)

Contacts

  • GSI - Kicker-Section
    • Udo Blell
    • Isfried Petzenhauser
  • GSI - CSCO
    • Alexander Bauer (Hardware)
    • Matthias Thieme (Hardware)
    • Alexander Schwinn (Software)
  • RI (formerly Ampegon)
    • Thomas Pfeiffer (PLC-controls + ? ) (to be checked, is still working for RI ?)
    • Michael Osemann (to be checked, is still working for RI ?)

Overview

  • Eack Kicker-Module (6 in total) will get its own SCU
  • Another Central SCU will generate trigger Signals for the Main and Dump Thyrantron of each Kicker Module (12 Signal cables in total)
  • All SCU's will have a WR-Timing receiver and will need to do multiplexed operations.
  • Each Kickermodule has a Main+dump Tyhratron, a main+dump Tank and a magnetron (MAG).
  • In order to generate the according silecs-model, each Kicker-Module, Tyhratron and Tank got it's own FESA-class. On top there is class "SIS100InjKicker" which describes the kicker as a whole.

FAT ( Factory acceptance Test)

  • The SCU crate for the FAT looks different than the final crate. Thw final crate will lack some cards (Trigger generation will be done by central SCU @ GSI)
  • Two SCUs will be sent to Ampegon, see [[https://www-acc.gsi.de/wiki/FESA/SIS100InjectionKickerFAT#A_42Netzger_228t_und_Thyratron_Pulse_steuern_42][details here].
  • The objective of the SCU-crate is the control of the HV power-supply, the generation of thyratron-pulses and to establish a connection to the PLC via silecs
  • A command line client will be provided to control the scu-crate and read all PLC information
  • The SCU will boot a Linux from USB which consists of all required sources and tools to compile / debug them
  • The first SCU-crate was sent to Ampegon in Dec. 2017, the second one should be sent to RI (new company) in mid 2021.

TODO

  • Integrate FESL Device into FESA Kicker Mod class (https://git.acc.gsi.de/fesa-classes/SIS100InjKicker/src/branch/master/SIS100InjKickerMod)
    • Is it required to Instantiate a fake "SIS100InjKicker" (the central part) on each FEC ?
  • So far Missing: FESA class which runs on the central SCU to generate the Signals (Configure signal length and delay)
    • A Separate FESA DU which only instantiates the "SIS100InjKicker" ?
    • Or no PLC connection at all for the central part, global info obtaind via global-device of each module ?
    • Does it make sense to re-use the same Deploy-Unit ? (Looks like we dont need to add devices for the module classes in the FESA instance file)
  • Manage Silecs connection of different deploys
    • One Deploy running per Kickermodule
    • Test: Can all of them connect to same PLC ? ( 6 connections ) --> Tested with CLI client --> No problem
    • Use SIS100InjKickerDU to generate one param file for all devices ( dont use separate DU for generation of .param file )
    • Add one instance-file per module
      • Each module binary has 1x Module, 2xTank, 2xThyr Device
      • Use global device for MAG ? Or use MAG_1 .. MAG_6 ?
      • MAG class triggers the periodic PLC readout and fills info's of all slave-classes ( Dont use default silecs methods to fill data ! )
  • All data should be available on PowerSupply level ( as well Data of Master)
  • Readout Magnet current Probe * ADC card ? Ask M.Thieme / A.Bauer
  • Need to read IEC 61076-2-101 M12 connector, 5 poles ?
    • Ask M.Thieme / A.Bauer
  • Interlock handling ( Gibt's auch auf den Bus-Slave interlocks ? )
  • Ask Kicker-Section which status-bits should generate a hardware interlock
  • WR-Events in FESL + FESA (on central SCU or on each Module SCU ? ):
    • start cable load
    • stop cable load (HVPS = 0V) + Meas voltage
    • Kick
    • Meas Magnet current probe during kick ?
    • ?
Topic revision: r30 - 20 Sep 2021, AlexanderSchwinn
This site is powered by FoswikiCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding Foswiki? Send feedback